* Chia-I Wu <olv@lunarg.com>
*/
-#include "util/u_surface.h"
-#include "util/u_transfer.h"
-#include "util/u_format_etc.h"
+#include "core/ilo_state_vf.h"
+#include "core/ilo_state_sol.h"
+#include "core/ilo_state_surface.h"
-#include "ilo_cp.h"
-#include "ilo_context.h"
#include "ilo_screen.h"
#include "ilo_resource.h"
-/* use PIPE_BIND_CUSTOM to indicate MCS */
-#define ILO_BIND_MCS PIPE_BIND_CUSTOM
-
-enum ilo_transfer_map_method {
- ILO_TRANSFER_MAP_DIRECT,
- ILO_TRANSFER_MAP_STAGING_SYS,
-};
-
-struct ilo_transfer {
- struct pipe_transfer base;
-
- enum ilo_transfer_map_method method;
- void *ptr;
-
- void *staging_sys;
-};
-
-static inline struct ilo_transfer *
-ilo_transfer(struct pipe_transfer *transfer)
-{
- return (struct ilo_transfer *) transfer;
-}
-
-static struct intel_bo *
-alloc_buf_bo(const struct ilo_resource *res)
-{
- struct ilo_screen *is = ilo_screen(res->base.screen);
- struct intel_bo *bo;
- const char *name;
- const unsigned size = res->bo_width;
-
- switch (res->base.bind) {
- case PIPE_BIND_VERTEX_BUFFER:
- name = "vertex buffer";
- break;
- case PIPE_BIND_INDEX_BUFFER:
- name = "index buffer";
- break;
- case PIPE_BIND_CONSTANT_BUFFER:
- name = "constant buffer";
- break;
- case PIPE_BIND_STREAM_OUTPUT:
- name = "stream output";
- break;
- default:
- name = "unknown buffer";
- break;
- }
-
- /* this is what a buffer supposed to be like */
- assert(res->bo_width * res->bo_height * res->bo_cpp == size);
- assert(res->tiling == INTEL_TILING_NONE);
- assert(res->bo_stride == 0);
-
- if (res->handle) {
- bo = is->winsys->import_handle(is->winsys, name,
- res->bo_width, res->bo_height, res->bo_cpp, res->handle);
-
- /* since the bo is shared to us, make sure it meets the expectations */
- if (bo) {
- assert(bo->get_size(res->bo) == size);
- assert(bo->get_tiling(res->bo) == res->tiling);
- assert(bo->get_pitch(res->bo) == res->bo_stride);
+/*
+ * From the Ivy Bridge PRM, volume 1 part 1, page 105:
+ *
+ * "In addition to restrictions on maximum height, width, and depth,
+ * surfaces are also restricted to a maximum size in bytes. This
+ * maximum is 2 GB for all products and all surface types."
+ */
+static const size_t ilo_max_resource_size = 1u << 31;
+
+static const char *
+resource_get_bo_name(const struct pipe_resource *templ)
+{
+ static const char *target_names[PIPE_MAX_TEXTURE_TYPES] = {
+ [PIPE_BUFFER] = "buf",
+ [PIPE_TEXTURE_1D] = "tex-1d",
+ [PIPE_TEXTURE_2D] = "tex-2d",
+ [PIPE_TEXTURE_3D] = "tex-3d",
+ [PIPE_TEXTURE_CUBE] = "tex-cube",
+ [PIPE_TEXTURE_RECT] = "tex-rect",
+ [PIPE_TEXTURE_1D_ARRAY] = "tex-1d-array",
+ [PIPE_TEXTURE_2D_ARRAY] = "tex-2d-array",
+ [PIPE_TEXTURE_CUBE_ARRAY] = "tex-cube-array",
+ };
+ const char *name = target_names[templ->target];
+
+ if (templ->target == PIPE_BUFFER) {
+ switch (templ->bind) {
+ case PIPE_BIND_VERTEX_BUFFER:
+ name = "buf-vb";
+ break;
+ case PIPE_BIND_INDEX_BUFFER:
+ name = "buf-ib";
+ break;
+ case PIPE_BIND_CONSTANT_BUFFER:
+ name = "buf-cb";
+ break;
+ case PIPE_BIND_STREAM_OUTPUT:
+ name = "buf-so";
+ break;
+ default:
+ break;
}
}
- else {
- bo = is->winsys->alloc_buffer(is->winsys, name, size, 0);
- }
- return bo;
+ return name;
}
-static struct intel_bo *
-alloc_tex_bo(const struct ilo_resource *res)
+static bool
+resource_get_cpu_init(const struct pipe_resource *templ)
{
- struct ilo_screen *is = ilo_screen(res->base.screen);
- struct intel_bo *bo;
- const char *name;
+ return (templ->bind & (PIPE_BIND_DEPTH_STENCIL |
+ PIPE_BIND_RENDER_TARGET |
+ PIPE_BIND_STREAM_OUTPUT)) ? false : true;
+}
- switch (res->base.target) {
+static enum gen_surface_type
+get_surface_type(enum pipe_texture_target target)
+{
+ switch (target) {
case PIPE_TEXTURE_1D:
- name = "1D texture";
- break;
+ case PIPE_TEXTURE_1D_ARRAY:
+ return GEN6_SURFTYPE_1D;
case PIPE_TEXTURE_2D:
- name = "2D texture";
- break;
- case PIPE_TEXTURE_3D:
- name = "3D texture";
- break;
- case PIPE_TEXTURE_CUBE:
- name = "cube texture";
- break;
case PIPE_TEXTURE_RECT:
- name = "rectangle texture";
- break;
- case PIPE_TEXTURE_1D_ARRAY:
- name = "1D array texture";
- break;
case PIPE_TEXTURE_2D_ARRAY:
- name = "2D array texture";
- break;
+ return GEN6_SURFTYPE_2D;
+ case PIPE_TEXTURE_3D:
+ return GEN6_SURFTYPE_3D;
+ case PIPE_TEXTURE_CUBE:
case PIPE_TEXTURE_CUBE_ARRAY:
- name = "cube array texture";
- break;
+ return GEN6_SURFTYPE_CUBE;
default:
- name ="unknown texture";
- break;
- }
-
- if (res->handle) {
- bo = is->winsys->import_handle(is->winsys, name,
- res->bo_width, res->bo_height, res->bo_cpp, res->handle);
- }
- else {
- const bool for_render =
- (res->base.bind & (PIPE_BIND_DEPTH_STENCIL |
- PIPE_BIND_RENDER_TARGET));
- const unsigned long flags =
- (for_render) ? INTEL_ALLOC_FOR_RENDER : 0;
-
- bo = is->winsys->alloc(is->winsys, name,
- res->bo_width, res->bo_height, res->bo_cpp,
- res->tiling, flags);
+ assert(!"unknown texture target");
+ return GEN6_SURFTYPE_NULL;
}
-
- return bo;
}
-static bool
-realloc_bo(struct ilo_resource *res)
+static enum pipe_format
+resource_get_image_format(const struct pipe_resource *templ,
+ const struct ilo_dev *dev,
+ bool *separate_stencil_ret)
{
- struct intel_bo *old_bo = res->bo;
+ enum pipe_format format = templ->format;
+ bool separate_stencil;
- /* a shared bo cannot be reallocated */
- if (old_bo && res->handle)
- return false;
-
- if (res->base.target == PIPE_BUFFER)
- res->bo = alloc_buf_bo(res);
- else
- res->bo = alloc_tex_bo(res);
+ /* silently promote ETC1 */
+ if (templ->format == PIPE_FORMAT_ETC1_RGB8)
+ format = PIPE_FORMAT_R8G8B8X8_UNORM;
- if (!res->bo) {
- res->bo = old_bo;
- return false;
+ /* separate stencil buffers */
+ separate_stencil = false;
+ if ((templ->bind & PIPE_BIND_DEPTH_STENCIL) &&
+ util_format_is_depth_and_stencil(templ->format)) {
+ switch (templ->format) {
+ case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
+ /* Gen6 requires HiZ to be available for all levels */
+ if (ilo_dev_gen(dev) >= ILO_GEN(7) || templ->last_level == 0) {
+ format = PIPE_FORMAT_Z32_FLOAT;
+ separate_stencil = true;
+ }
+ break;
+ case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ format = PIPE_FORMAT_Z24X8_UNORM;
+ separate_stencil = true;
+ break;
+ default:
+ break;
+ }
}
- /* winsys may decide to use a different tiling */
- res->tiling = res->bo->get_tiling(res->bo);
- res->bo_stride = res->bo->get_pitch(res->bo);
+ if (separate_stencil_ret)
+ *separate_stencil_ret = separate_stencil;
- if (old_bo)
- old_bo->unreference(old_bo);
-
- return true;
+ return format;
}
static void
-ilo_transfer_inline_write(struct pipe_context *pipe,
- struct pipe_resource *r,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box,
- const void *data,
- unsigned stride,
- unsigned layer_stride)
+resource_get_image_info(const struct pipe_resource *templ,
+ const struct ilo_dev *dev,
+ enum pipe_format image_format,
+ struct ilo_image_info *info)
{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_resource *res = ilo_resource(r);
- int offset, size;
- bool will_be_busy;
-
- /*
- * Fall back to map(), memcpy(), and unmap(). We use this path for
- * unsynchronized write, as the buffer is likely to be busy and pwrite()
- * will stall.
- */
- if (unlikely(res->base.target != PIPE_BUFFER) ||
- (usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
- u_default_transfer_inline_write(pipe, r,
- level, usage, box, data, stride, layer_stride);
+ memset(info, 0, sizeof(*info));
- return;
- }
+ info->type = get_surface_type(templ->target);
+ info->format = image_format;
- /*
- * XXX With hardware context support, the bo may be needed by GPU without
- * being referenced by ilo->cp->bo. We have to flush unconditionally, and
- * that is bad.
- */
- if (ilo->cp->hw_ctx)
- ilo_cp_flush(ilo->cp);
+ info->width = templ->width0;
+ info->height = templ->height0;
+ info->depth = templ->depth0;
+ info->array_size = templ->array_size;
+ info->level_count = templ->last_level + 1;
+ info->sample_count = (templ->nr_samples) ? templ->nr_samples : 1;
- will_be_busy = ilo->cp->bo->references(ilo->cp->bo, res->bo);
+ info->aux_disable = (templ->usage == PIPE_USAGE_STAGING);
- /* see if we can avoid stalling */
- if (will_be_busy || intel_bo_is_busy(res->bo)) {
- bool will_stall = true;
+ if (templ->bind & PIPE_BIND_LINEAR)
+ info->valid_tilings = 1 << GEN6_TILING_NONE;
- if (usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
- /* old data not needed so discard the old bo to avoid stalling */
- if (realloc_bo(res))
- will_stall = false;
- }
- else {
- /*
- * We could allocate a temporary bo to hold the data and emit
- * pipelined copy blit to move them to res->bo. But for now, do
- * nothing.
- */
- }
+ info->bind_surface_sampler = (templ->bind & PIPE_BIND_SAMPLER_VIEW);
+ info->bind_surface_dp_render = (templ->bind & PIPE_BIND_RENDER_TARGET);
+ info->bind_surface_dp_typed = (templ->bind &
+ (PIPE_BIND_SHADER_RESOURCE | PIPE_BIND_COMPUTE_RESOURCE));
+ info->bind_zs = (templ->bind & PIPE_BIND_DEPTH_STENCIL);
+ info->bind_scanout = (templ->bind & PIPE_BIND_SCANOUT);
+ info->bind_cursor = (templ->bind & PIPE_BIND_CURSOR);
+}
- /* flush to make bo busy (so that pwrite() stalls as it should be) */
- if (will_stall && will_be_busy)
- ilo_cp_flush(ilo->cp);
+static enum gen_surface_tiling
+winsys_to_surface_tiling(enum intel_tiling_mode tiling)
+{
+ switch (tiling) {
+ case INTEL_TILING_NONE:
+ return GEN6_TILING_NONE;
+ case INTEL_TILING_X:
+ return GEN6_TILING_X;
+ case INTEL_TILING_Y:
+ return GEN6_TILING_Y;
+ default:
+ assert(!"unknown tiling");
+ return GEN6_TILING_NONE;
}
-
- /* for PIPE_BUFFERs, conversion should not be needed */
- assert(res->bo_format == res->base.format);
-
- /* they should specify just an offset and a size */
- assert(level == 0);
- assert(box->y == 0);
- assert(box->z == 0);
- assert(box->height == 1);
- assert(box->depth == 1);
- offset = box->x;
- size = box->width;
-
- res->bo->pwrite(res->bo, offset, size, data);
}
-static void
-transfer_unmap_sys_convert(enum pipe_format dst_fmt,
- const struct pipe_transfer *dst_xfer,
- void *dst,
- enum pipe_format src_fmt,
- const struct pipe_transfer *src_xfer,
- const void *src)
+static inline enum intel_tiling_mode
+surface_to_winsys_tiling(enum gen_surface_tiling tiling)
{
- int i;
-
- switch (src_fmt) {
- case PIPE_FORMAT_ETC1_RGB8:
- assert(dst_fmt == PIPE_FORMAT_R8G8B8X8_UNORM);
-
- for (i = 0; i < dst_xfer->box.depth; i++) {
- util_format_etc1_rgb8_unpack_rgba_8unorm(dst,
- dst_xfer->stride, src, src_xfer->stride,
- dst_xfer->box.width, dst_xfer->box.height);
-
- dst += dst_xfer->layer_stride;
- src += src_xfer->layer_stride;
- }
- break;
+ switch (tiling) {
+ case GEN6_TILING_NONE:
+ return INTEL_TILING_NONE;
+ case GEN6_TILING_X:
+ return INTEL_TILING_X;
+ case GEN6_TILING_Y:
+ return INTEL_TILING_Y;
default:
- assert(!"unable to convert the staging data");
- break;
+ assert(!"unknown tiling");
+ return GEN6_TILING_NONE;
}
}
static void
-transfer_unmap_sys(struct ilo_context *ilo,
- struct ilo_resource *res,
- struct ilo_transfer *xfer)
+tex_free_slices(struct ilo_texture *tex)
{
- const void *src = xfer->ptr;
- struct pipe_transfer *dst_xfer;
- void *dst;
-
- dst = ilo->base.transfer_map(&ilo->base,
- xfer->base.resource, xfer->base.level,
- PIPE_TRANSFER_WRITE |
- PIPE_TRANSFER_MAP_DIRECTLY |
- PIPE_TRANSFER_DISCARD_RANGE,
- &xfer->base.box, &dst_xfer);
- if (!dst_xfer) {
- ilo_err("failed to map resource for moving staging data\n");
- FREE(xfer->staging_sys);
- return;
- }
-
- if (likely(res->bo_format != res->base.format)) {
- transfer_unmap_sys_convert(res->bo_format, dst_xfer, dst,
- res->base.format, &xfer->base, src);
- }
- else {
- util_copy_box(dst, res->bo_format,
- dst_xfer->stride, dst_xfer->layer_stride, 0, 0, 0,
- dst_xfer->box.width, dst_xfer->box.height, dst_xfer->box.depth,
- src, xfer->base.stride, xfer->base.layer_stride, 0, 0, 0);
- }
-
- ilo->base.transfer_unmap(&ilo->base, dst_xfer);
- FREE(xfer->staging_sys);
+ FREE(tex->slices[0]);
}
static bool
-transfer_map_sys(struct ilo_context *ilo,
- struct ilo_resource *res,
- struct ilo_transfer *xfer)
+tex_alloc_slices(struct ilo_texture *tex)
{
- const struct pipe_box *box = &xfer->base.box;
- const size_t stride = util_format_get_stride(res->base.format, box->width);
- const size_t size =
- util_format_get_2d_size(res->base.format, stride, box->height);
- bool read_back;
-
- if (xfer->base.usage & PIPE_TRANSFER_READ) {
- read_back = true;
- }
- else if (xfer->base.usage & PIPE_TRANSFER_WRITE) {
- const unsigned discard_flags =
- (PIPE_TRANSFER_DISCARD_RANGE | PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE);
+ const struct pipe_resource *templ = &tex->base;
+ struct ilo_texture_slice *slices;
+ int depth, lv;
- if (!(xfer->base.usage & discard_flags))
- read_back = true;
- }
+ /* sum the depths of all levels */
+ depth = 0;
+ for (lv = 0; lv <= templ->last_level; lv++)
+ depth += u_minify(templ->depth0, lv);
- /* TODO */
- if (read_back)
+ /*
+ * There are (depth * tex->base.array_size) slices in total. Either depth
+ * is one (non-3D) or templ->array_size is one (non-array), but it does
+ * not matter.
+ */
+ slices = CALLOC(depth * templ->array_size, sizeof(*slices));
+ if (!slices)
return false;
- xfer->staging_sys = MALLOC(size * box->depth);
- if (!xfer->staging_sys)
- return false;
+ tex->slices[0] = slices;
- xfer->base.stride = stride;
- xfer->base.layer_stride = size;
- xfer->ptr = xfer->staging_sys;
+ /* point to the respective positions in the buffer */
+ for (lv = 1; lv <= templ->last_level; lv++) {
+ tex->slices[lv] = tex->slices[lv - 1] +
+ u_minify(templ->depth0, lv - 1) * templ->array_size;
+ }
return true;
}
-static void
-transfer_unmap_direct(struct ilo_context *ilo,
- struct ilo_resource *res,
- struct ilo_transfer *xfer)
-{
- res->bo->unmap(res->bo);
-}
-
static bool
-transfer_map_direct(struct ilo_context *ilo,
- struct ilo_resource *res,
- struct ilo_transfer *xfer)
+tex_create_bo(struct ilo_texture *tex)
{
- int x, y, err;
-
- if (xfer->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED)
- err = res->bo->map_unsynchronized(res->bo);
- /* prefer map() when there is the last-level cache */
- else if (res->tiling == INTEL_TILING_NONE &&
- (ilo->dev->has_llc || (xfer->base.usage & PIPE_TRANSFER_READ)))
- err = res->bo->map(res->bo, (xfer->base.usage & PIPE_TRANSFER_WRITE));
- else
- err = res->bo->map_gtt(res->bo);
-
- if (err)
- return false;
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ const char *name = resource_get_bo_name(&tex->base);
+ const bool cpu_init = resource_get_cpu_init(&tex->base);
+ struct intel_bo *bo;
- /* note that stride is for a block row, not a texel row */
- xfer->base.stride = res->bo_stride;
+ bo = intel_winsys_alloc_bo(is->dev.winsys, name,
+ tex->image.bo_stride * tex->image.bo_height, cpu_init);
- /*
- * we can walk through layers when the resource is a texture array or
- * when this is the first level of a 3D texture being mapped
- */
- if (res->base.array_size > 1 ||
- (res->base.target == PIPE_TEXTURE_3D && xfer->base.level == 0)) {
- const unsigned qpitch = res->slice_offsets[xfer->base.level][1].y -
- res->slice_offsets[xfer->base.level][0].y;
+ /* set the tiling for transfer and export */
+ if (bo && (tex->image.tiling == GEN6_TILING_X ||
+ tex->image.tiling == GEN6_TILING_Y)) {
+ const enum intel_tiling_mode tiling =
+ surface_to_winsys_tiling(tex->image.tiling);
- assert(qpitch % res->block_height == 0);
- xfer->base.layer_stride = (qpitch / res->block_height) * xfer->base.stride;
- }
- else {
- xfer->base.layer_stride = 0;
+ if (intel_bo_set_tiling(bo, tiling, tex->image.bo_stride)) {
+ intel_bo_unref(bo);
+ bo = NULL;
+ }
}
+ if (!bo)
+ return false;
- x = res->slice_offsets[xfer->base.level][xfer->base.box.z].x;
- y = res->slice_offsets[xfer->base.level][xfer->base.box.z].y;
-
- x += xfer->base.box.x;
- y += xfer->base.box.y;
-
- /* in blocks */
- assert(x % res->block_width == 0 && y % res->block_height == 0);
- x /= res->block_width;
- y /= res->block_height;
-
- xfer->ptr = res->bo->get_virtual(res->bo);
- xfer->ptr += y * res->bo_stride + x * res->bo_cpp;
+ intel_bo_unref(tex->vma.bo);
+ ilo_vma_set_bo(&tex->vma, &is->dev, bo, 0);
return true;
}
-/**
- * Choose the best mapping method, depending on the transfer usage and whether
- * the bo is busy.
- */
static bool
-transfer_map_choose_method(struct ilo_context *ilo,
- struct ilo_resource *res,
- struct ilo_transfer *xfer)
+tex_create_separate_stencil(struct ilo_texture *tex)
{
- bool will_be_busy, will_stall;
-
- /* need to convert on-the-fly */
- if (res->bo_format != res->base.format &&
- !(xfer->base.usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
- xfer->method = ILO_TRANSFER_MAP_STAGING_SYS;
-
- return true;
- }
-
- xfer->method = ILO_TRANSFER_MAP_DIRECT;
-
- /* unsynchronized map does not stall */
- if (xfer->base.usage & PIPE_TRANSFER_UNSYNCHRONIZED)
- return true;
-
- will_be_busy = ilo->cp->bo->references(ilo->cp->bo, res->bo);
- if (!will_be_busy) {
- /*
- * XXX With hardware context support, the bo may be needed by GPU
- * without being referenced by ilo->cp->bo. We have to flush
- * unconditionally, and that is bad.
- */
- if (ilo->cp->hw_ctx)
- ilo_cp_flush(ilo->cp);
+ struct pipe_resource templ = tex->base;
+ struct pipe_resource *s8;
- if (!intel_bo_is_busy(res->bo))
- return true;
- }
+ /*
+ * Unless PIPE_BIND_DEPTH_STENCIL is set, the resource may have other
+ * tilings. But that should be fine since it will never be bound as the
+ * stencil buffer, and our transfer code can handle all tilings.
+ */
+ templ.format = PIPE_FORMAT_S8_UINT;
- /* bo is busy and mapping it will stall */
- will_stall = true;
+ /* no stencil texturing */
+ templ.bind &= ~PIPE_BIND_SAMPLER_VIEW;
- if (xfer->base.usage & PIPE_TRANSFER_MAP_DIRECTLY) {
- /* nothing we can do */
- }
- else if (xfer->base.usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE) {
- /* discard old bo and allocate a new one for mapping */
- if (realloc_bo(res))
- will_stall = false;
- }
- else if (xfer->base.usage & PIPE_TRANSFER_FLUSH_EXPLICIT) {
- /*
- * We could allocate and return a system buffer here. When a region of
- * the buffer is explicitly flushed, we pwrite() the region to a
- * temporary bo and emit pipelined copy blit.
- *
- * For now, do nothing.
- */
- }
- else if (xfer->base.usage & PIPE_TRANSFER_DISCARD_RANGE) {
- /*
- * We could allocate a temporary bo for mapping, and emit pipelined copy
- * blit upon unmapping.
- *
- * For now, do nothing.
- */
- }
+ s8 = tex->base.screen->resource_create(tex->base.screen, &templ);
+ if (!s8)
+ return false;
- if (will_stall) {
- if (xfer->base.usage & PIPE_TRANSFER_DONTBLOCK)
- return false;
+ tex->separate_s8 = ilo_texture(s8);
- /* flush to make bo busy (so that map() stalls as it should be) */
- if (will_be_busy)
- ilo_cp_flush(ilo->cp);
- }
+ assert(tex->separate_s8->image.format == PIPE_FORMAT_S8_UINT);
return true;
}
-static void
-ilo_transfer_flush_region(struct pipe_context *pipe,
- struct pipe_transfer *transfer,
- const struct pipe_box *box)
+static bool
+tex_create_hiz(struct ilo_texture *tex)
{
-}
+ const struct pipe_resource *templ = &tex->base;
+ const uint32_t size = tex->image.aux.bo_stride * tex->image.aux.bo_height;
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ struct intel_bo *bo;
-static void
-ilo_transfer_unmap(struct pipe_context *pipe,
- struct pipe_transfer *transfer)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_resource *res = ilo_resource(transfer->resource);
- struct ilo_transfer *xfer = ilo_transfer(transfer);
+ bo = intel_winsys_alloc_bo(is->dev.winsys, "hiz texture", size, false);
+ if (!bo)
+ return false;
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_DIRECT:
- transfer_unmap_direct(ilo, res, xfer);
- break;
- case ILO_TRANSFER_MAP_STAGING_SYS:
- transfer_unmap_sys(ilo, res, xfer);
- break;
- default:
- assert(!"unknown mapping method");
- break;
- }
+ ilo_vma_init(&tex->aux_vma, &is->dev, size, 4096);
+ ilo_vma_set_bo(&tex->aux_vma, &is->dev, bo, 0);
- pipe_resource_reference(&xfer->base.resource, NULL);
- FREE(xfer);
-}
+ if (tex->imported) {
+ unsigned lv;
-static void *
-ilo_transfer_map(struct pipe_context *pipe,
- struct pipe_resource *r,
- unsigned level,
- unsigned usage,
- const struct pipe_box *box,
- struct pipe_transfer **transfer)
-{
- struct ilo_context *ilo = ilo_context(pipe);
- struct ilo_resource *res = ilo_resource(r);
- struct ilo_transfer *xfer;
- int ok;
-
- xfer = MALLOC_STRUCT(ilo_transfer);
- if (!xfer) {
- *transfer = NULL;
- return NULL;
- }
+ for (lv = 0; lv <= templ->last_level; lv++) {
+ if (tex->image.aux.enables & (1 << lv)) {
+ const unsigned num_slices = (templ->target == PIPE_TEXTURE_3D) ?
+ u_minify(templ->depth0, lv) : templ->array_size;
+ /* this will trigger HiZ resolves */
+ const unsigned flags = ILO_TEXTURE_CPU_WRITE;
- xfer->base.resource = NULL;
- pipe_resource_reference(&xfer->base.resource, &res->base);
- xfer->base.level = level;
- xfer->base.usage = usage;
- xfer->base.box = *box;
-
- ok = transfer_map_choose_method(ilo, res, xfer);
- if (ok) {
- switch (xfer->method) {
- case ILO_TRANSFER_MAP_DIRECT:
- ok = transfer_map_direct(ilo, res, xfer);
- break;
- case ILO_TRANSFER_MAP_STAGING_SYS:
- ok = transfer_map_sys(ilo, res, xfer);
- break;
- default:
- assert(!"unknown mapping method");
- ok = false;
- break;
+ ilo_texture_set_slice_flags(tex, lv, 0, num_slices, flags, flags);
+ }
}
}
- if (!ok) {
- pipe_resource_reference(&xfer->base.resource, NULL);
- FREE(xfer);
-
- *transfer = NULL;
-
- return NULL;
- }
-
- *transfer = &xfer->base;
-
- return xfer->ptr;
+ return true;
}
static bool
-alloc_slice_offsets(struct ilo_resource *res)
+tex_create_mcs(struct ilo_texture *tex)
{
- int depth, lv;
+ const uint32_t size = tex->image.aux.bo_stride * tex->image.aux.bo_height;
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ struct intel_bo *bo;
- /* sum the depths of all levels */
- depth = 0;
- for (lv = 0; lv <= res->base.last_level; lv++)
- depth += u_minify(res->base.depth0, lv);
+ assert(tex->image.aux.enables == (1 << (tex->base.last_level + 1)) - 1);
- /*
- * There are (depth * res->base.array_size) slices. Either depth is one
- * (non-3D) or res->base.array_size is one (non-array), but it does not
- * matter.
- */
- res->slice_offsets[0] =
- CALLOC(depth * res->base.array_size, sizeof(res->slice_offsets[0][0]));
- if (!res->slice_offsets[0])
+ bo = intel_winsys_alloc_bo(is->dev.winsys, "mcs texture", size, false);
+ if (!bo)
return false;
- /* point to the respective positions in the buffer */
- for (lv = 1; lv <= res->base.last_level; lv++) {
- res->slice_offsets[lv] = res->slice_offsets[lv - 1] +
- u_minify(res->base.depth0, lv - 1) * res->base.array_size;
- }
+ ilo_vma_init(&tex->aux_vma, &is->dev, size, 4096);
+ ilo_vma_set_bo(&tex->aux_vma, &is->dev, bo, 0);
return true;
}
static void
-free_slice_offsets(struct ilo_resource *res)
+tex_destroy(struct ilo_texture *tex)
{
- int lv;
-
- FREE(res->slice_offsets[0]);
- for (lv = 0; lv <= res->base.last_level; lv++)
- res->slice_offsets[lv] = NULL;
-}
+ if (tex->separate_s8)
+ tex_destroy(tex->separate_s8);
-struct layout_tex_info {
- bool compressed;
- int block_width, block_height;
- int align_i, align_j;
- bool array_spacing_full;
- bool interleaved;
- int qpitch;
+ intel_bo_unref(tex->vma.bo);
+ intel_bo_unref(tex->aux_vma.bo);
- struct {
- int w, h, d;
- } sizes[PIPE_MAX_TEXTURE_LEVELS];
-};
+ tex_free_slices(tex);
+ FREE(tex);
+}
-/**
- * Prepare for texture layout.
- */
-static void
-layout_tex_init(const struct ilo_resource *res, struct layout_tex_info *info)
+static bool
+tex_alloc_bos(struct ilo_texture *tex)
{
- struct ilo_screen *is = ilo_screen(res->base.screen);
- const enum pipe_format bo_format = res->bo_format;
- const enum intel_tiling_mode tiling = res->tiling;
- const struct pipe_resource *templ = &res->base;
- int last_level, lv;
+ if (!tex->imported && !tex_create_bo(tex))
+ return false;
- memset(info, 0, sizeof(*info));
+ switch (tex->image.aux.type) {
+ case ILO_IMAGE_AUX_HIZ:
+ if (!tex_create_hiz(tex))
+ return false;
+ break;
+ case ILO_IMAGE_AUX_MCS:
+ if (!tex_create_mcs(tex))
+ return false;
+ break;
+ default:
+ break;
+ }
- info->compressed = util_format_is_compressed(bo_format);
- info->block_width = util_format_get_blockwidth(bo_format);
- info->block_height = util_format_get_blockheight(bo_format);
+ return true;
+}
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 113:
- *
- * "surface format align_i align_j
- * YUV 4:2:2 formats 4 *see below
- * BC1-5 4 4
- * FXT1 8 4
- * all other formats 4 *see below"
- *
- * "- align_j = 4 for any depth buffer
- * - align_j = 2 for separate stencil buffer
- * - align_j = 4 for any render target surface is multisampled (4x)
- * - align_j = 4 for any render target surface with Surface Vertical
- * Alignment = VALIGN_4
- * - align_j = 2 for any render target surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 2 for all other render target surface
- * - align_j = 2 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_2
- * - align_j = 4 for any sampling engine surface with Surface Vertical
- * Alignment = VALIGN_4"
- *
- * From the Sandy Bridge PRM, volume 4 part 1, page 86:
- *
- * "This field (Surface Vertical Alignment) must be set to VALIGN_2 if
- * the Surface Format is 96 bits per element (BPE)."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * PIPE_FORMAT_S8_UINT 4 2
- * other depth/stencil formats 4 4
- * 4x multisampled 4 4
- * bpp 96 4 2
- * others 4 2 or 4
- */
+static struct intel_bo *
+tex_import_handle(struct ilo_texture *tex,
+ const struct winsys_handle *handle,
+ struct ilo_image_info *info)
+{
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ const struct pipe_resource *templ = &tex->base;
+ const char *name = resource_get_bo_name(&tex->base);
+ enum intel_tiling_mode tiling;
+ unsigned long pitch;
+ struct intel_bo *bo;
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 110:
- *
- * "surface defined by surface format align_i align_j
- * 3DSTATE_DEPTH_BUFFER D16_UNORM 8 4
- * not D16_UNORM 4 4
- * 3DSTATE_STENCIL_BUFFER N/A 8 8
- * SURFACE_STATE BC*, ETC*, EAC* 4 4
- * FXT1 8 4
- * all others (set by SURFACE_STATE)"
- *
- * From the Ivy Bridge PRM, volume 4 part 1, page 63:
- *
- * "- This field (Surface Vertical Aligment) is intended to be set to
- * VALIGN_4 if the surface was rendered as a depth buffer, for a
- * multisampled (4x) render target, or for a multisampled (8x)
- * render target, since these surfaces support only alignment of 4.
- * - Use of VALIGN_4 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to VALIGN_4 for all tiled Y Render Target
- * surfaces.
- * - Value of 1 is not supported for format YCRCB_NORMAL (0x182),
- * YCRCB_SWAPUVY (0x183), YCRCB_SWAPUV (0x18f), YCRCB_SWAPY (0x190)
- * - If Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * must be set to VALIGN_4."
- * - VALIGN_4 is not supported for surface format R32G32B32_FLOAT."
- *
- * "- This field (Surface Horizontal Aligment) is intended to be set to
- * HALIGN_8 only if the surface was rendered as a depth buffer with
- * Z16 format or a stencil buffer, since these surfaces support only
- * alignment of 8.
- * - Use of HALIGN_8 for other surfaces is supported, but uses more
- * memory.
- * - This field must be set to HALIGN_4 if the Surface Format is BC*.
- * - This field must be set to HALIGN_8 if the Surface Format is
- * FXT1."
- *
- * They can be rephrased as
- *
- * align_i align_j
- * compressed formats block width block height
- * PIPE_FORMAT_Z16_UNORM 8 4
- * PIPE_FORMAT_S8_UINT 8 8
- * other depth/stencil formats 4 or 8 4
- * 2x or 4x multisampled 4 or 8 4
- * tiled Y 4 or 8 4 (if rt)
- * PIPE_FORMAT_R32G32B32_FLOAT 4 or 8 2
- * others 4 or 8 2 or 4
- */
+ bo = intel_winsys_import_handle(is->dev.winsys, name, handle,
+ tex->image.bo_height, &tiling, &pitch);
+ /* modify image info */
+ if (bo) {
+ const uint8_t valid_tilings = 1 << winsys_to_surface_tiling(tiling);
- if (info->compressed) {
- /* this happens to be the case */
- info->align_i = info->block_width;
- info->align_j = info->block_height;
- }
- else if (util_format_is_depth_or_stencil(bo_format)) {
- if (is->dev.gen >= ILO_GEN(7)) {
- switch (bo_format) {
- case PIPE_FORMAT_Z16_UNORM:
- info->align_i = 8;
- info->align_j = 4;
- break;
- case PIPE_FORMAT_S8_UINT:
- info->align_i = 8;
- info->align_j = 8;
- break;
- default:
- /*
- * From the Ivy Bridge PRM, volume 2 part 1, page 319:
- *
- * "The 3 LSBs of both offsets (Depth Coordinate Offset Y and
- * Depth Coordinate Offset X) must be zero to ensure correct
- * alignment"
- *
- * We will make use of them and setting align_i to 8 help us meet
- * the requirement.
- */
- info->align_i = (templ->last_level > 0) ? 8 : 4;
- info->align_j = 4;
- break;
- }
- }
- else {
- switch (bo_format) {
- case PIPE_FORMAT_S8_UINT:
- info->align_i = 4;
- info->align_j = 2;
- break;
- default:
- info->align_i = 4;
- info->align_j = 4;
- break;
- }
+ if (info->valid_tilings && !(info->valid_tilings & valid_tilings)) {
+ intel_bo_unref(bo);
+ return NULL;
}
+
+ info->valid_tilings = valid_tilings;
+ info->force_bo_stride = pitch;
+
+ /* assume imported RTs are also scanouts */
+ if (!info->bind_scanout)
+ info->bind_scanout = (templ->usage & PIPE_BIND_RENDER_TARGET);
}
- else {
- const bool valign_4 = (templ->nr_samples > 1) ||
- (is->dev.gen >= ILO_GEN(7) &&
- (templ->bind & PIPE_BIND_RENDER_TARGET) &&
- tiling == INTEL_TILING_Y);
- if (valign_4)
- assert(util_format_get_blocksizebits(bo_format) != 96);
+ return bo;
+}
- info->align_i = 4;
- info->align_j = (valign_4) ? 4 : 2;
+static bool
+tex_init_image(struct ilo_texture *tex,
+ const struct winsys_handle *handle,
+ bool *separate_stencil)
+{
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ const struct pipe_resource *templ = &tex->base;
+ struct ilo_image *img = &tex->image;
+ struct intel_bo *imported_bo = NULL;;
+ enum pipe_format image_format;
+ struct ilo_image_info info;
+
+ image_format = resource_get_image_format(templ,
+ &is->dev, separate_stencil);
+ resource_get_image_info(templ, &is->dev, image_format, &info);
+
+ if (handle) {
+ imported_bo = tex_import_handle(tex, handle, &info);
+ if (!imported_bo)
+ return false;
+ }
+
+ if (!ilo_image_init(img, &is->dev, &info)) {
+ intel_bo_unref(imported_bo);
+ return false;
}
/*
- * the fact that align i and j are multiples of block width and height
- * respectively is what makes the size of the bo a multiple of the block
- * size, slices start at block boundaries, and many of the computations
- * work.
+ * HiZ requires 8x4 alignment and some levels might need HiZ disabled. It
+ * is generally fine except on Gen6, where HiZ and separate stencil must be
+ * enabled together. For PIPE_FORMAT_Z24X8_UNORM with separate stencil, we
+ * can live with stencil values being interleaved for levels where HiZ is
+ * disabled. But it is not the case for PIPE_FORMAT_Z32_FLOAT with
+ * separate stencil. If HiZ was disabled for a level, we had to change the
+ * format to PIPE_FORMAT_Z32_FLOAT_S8X24_UINT for the level and that format
+ * had a different bpp. In other words, HiZ has to be available for all
+ * levels.
*/
- assert(info->align_i % info->block_width == 0);
- assert(info->align_j % info->block_height == 0);
-
- /* make sure align() works */
- assert(util_is_power_of_two(info->align_i) &&
- util_is_power_of_two(info->align_j));
- assert(util_is_power_of_two(info->block_width) &&
- util_is_power_of_two(info->block_height));
-
- if (is->dev.gen >= ILO_GEN(7)) {
- /*
- * It is not explicitly states, but render targets are expected to be
- * UMS/CMS (samples non-interleaved) and depth/stencil buffers are
- * expected to be IMS (samples interleaved).
- *
- * See "Multisampled Surface Storage Format" field of SURFACE_STATE.
- */
- if (util_format_is_depth_or_stencil(bo_format)) {
- info->interleaved = true;
-
- /*
- * From the Ivy Bridge PRM, volume 1 part 1, page 111:
- *
- * "note that the depth buffer and stencil buffer have an implied
- * value of ARYSPC_FULL"
- */
- info->array_spacing_full = true;
- }
- else {
- info->interleaved = false;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 66:
- *
- * "If Multisampled Surface Storage Format is MSFMT_MSS and
- * Number of Multisamples is not MULTISAMPLECOUNT_1, this field
- * (Surface Array Spacing) must be set to ARYSPC_LOD0."
- *
- * As multisampled resources are not mipmapped, we never use
- * ARYSPC_FULL for them.
- */
- if (templ->nr_samples > 1)
- assert(templ->last_level == 0);
- info->array_spacing_full = (templ->last_level > 0);
+ if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
+ templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
+ image_format == PIPE_FORMAT_Z32_FLOAT &&
+ img->aux.enables != (1 << templ->last_level)) {
+ image_format = templ->format;
+ info.format = image_format;
+
+ memset(img, 0, sizeof(*img));
+ if (!ilo_image_init(img, &is->dev, &info)) {
+ intel_bo_unref(imported_bo);
+ return false;
}
}
- else {
- /* GEN6 supports only interleaved samples */
- info->interleaved = true;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The separate stencil buffer does not support mip mapping, thus
- * the storage for LODs other than LOD 0 is not needed. The
- * following QPitch equation applies only to the separate stencil
- * buffer:
- *
- * QPitch = h_0"
- *
- * GEN6 does not support compact spacing otherwise.
- */
- info->array_spacing_full = (bo_format != PIPE_FORMAT_S8_UINT);
- }
-
- last_level = templ->last_level;
-
- /* need at least 2 levels to compute full qpitch */
- if (last_level == 0 && templ->array_size > 1 && info->array_spacing_full)
- last_level++;
-
- /* compute mip level sizes */
- for (lv = 0; lv <= last_level; lv++) {
- int w, h, d;
-
- w = u_minify(templ->width0, lv);
- h = u_minify(templ->height0, lv);
- d = u_minify(templ->depth0, lv);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 114:
- *
- * "The dimensions of the mip maps are first determined by applying
- * the sizing algorithm presented in Non-Power-of-Two Mipmaps
- * above. Then, if necessary, they are padded out to compression
- * block boundaries."
- */
- w = align(w, info->block_width);
- h = align(h, info->block_height);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 111:
- *
- * "If the surface is multisampled (4x), these values must be
- * adjusted as follows before proceeding:
- *
- * W_L = ceiling(W_L / 2) * 4
- * H_L = ceiling(H_L / 2) * 4"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 108:
- *
- * "If the surface is multisampled and it is a depth or stencil
- * surface or Multisampled Surface StorageFormat in SURFACE_STATE
- * is MSFMT_DEPTH_STENCIL, W_L and H_L must be adjusted as follows
- * before proceeding:
- *
- * #samples W_L = H_L =
- * 2 ceiling(W_L / 2) * 4 HL [no adjustment]
- * 4 ceiling(W_L / 2) * 4 ceiling(H_L / 2) * 4
- * 8 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 4
- * 16 ceiling(W_L / 2) * 8 ceiling(H_L / 2) * 8"
- *
- * For interleaved samples (4x), where pixels
- *
- * (x, y ) (x+1, y )
- * (x, y+1) (x+1, y+1)
- *
- * would be is occupied by
- *
- * (x, y , si0) (x+1, y , si0) (x, y , si1) (x+1, y , si1)
- * (x, y+1, si0) (x+1, y+1, si0) (x, y+1, si1) (x+1, y+1, si1)
- * (x, y , si2) (x+1, y , si2) (x, y , si3) (x+1, y , si3)
- * (x, y+1, si2) (x+1, y+1, si2) (x, y+1, si3) (x+1, y+1, si3)
- *
- * Thus the need to
- *
- * w = align(w, 2) * 2;
- * y = align(y, 2) * 2;
- */
- if (info->interleaved) {
- switch (templ->nr_samples) {
- case 0:
- case 1:
- break;
- case 2:
- w = align(w, 2) * 2;
- break;
- case 4:
- w = align(w, 2) * 2;
- h = align(h, 2) * 2;
- break;
- case 8:
- w = align(w, 2) * 4;
- h = align(h, 2) * 2;
- break;
- case 16:
- w = align(w, 2) * 4;
- h = align(h, 2) * 4;
- break;
- default:
- assert(!"unsupported sample count");
- break;
- }
- }
- info->sizes[lv].w = w;
- info->sizes[lv].h = h;
- info->sizes[lv].d = d;
+ if (img->bo_height > ilo_max_resource_size / img->bo_stride ||
+ !ilo_vma_init(&tex->vma, &is->dev, img->bo_stride * img->bo_height,
+ 4096)) {
+ intel_bo_unref(imported_bo);
+ return false;
}
- if (templ->array_size > 1) {
- const int h0 = align(info->sizes[0].h, info->align_j);
-
- if (info->array_spacing_full) {
- const int h1 = align(info->sizes[1].h, info->align_j);
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 1, page 115:
- *
- * "The following equation is used for surface formats other than
- * compressed textures:
- *
- * QPitch = (h0 + h1 + 11j)"
- *
- * "The equation for compressed textures (BC* and FXT1 surface
- * formats) follows:
- *
- * QPitch = (h0 + h1 + 11j) / 4"
- *
- * "[DevSNB] Errata: Sampler MSAA Qpitch will be 4 greater than
- * the value calculated in the equation above, for every other
- * odd Surface Height starting from 1 i.e. 1,5,9,13"
- *
- * From the Ivy Bridge PRM, volume 1 part 1, page 111-112:
- *
- * "If Surface Array Spacing is set to ARYSPC_FULL (note that the
- * depth buffer and stencil buffer have an implied value of
- * ARYSPC_FULL):
- *
- * QPitch = (h0 + h1 + 12j)
- * QPitch = (h0 + h1 + 12j) / 4 (compressed)
- *
- * (There are many typos or missing words here...)"
- *
- * To access the N-th slice, an offset of (Stride * QPitch * N) is
- * added to the base address. The PRM divides QPitch by 4 for
- * compressed formats because the block height for those formats are
- * 4, and it wants QPitch to mean the number of memory rows, as
- * opposed to texel rows, between slices. Since we use texel rows in
- * res->slice_offsets, we do not need to divide QPitch by 4.
- */
- info->qpitch = h0 + h1 +
- ((is->dev.gen >= ILO_GEN(7)) ? 12 : 11) * info->align_j;
-
- if (is->dev.gen == ILO_GEN(6) && templ->nr_samples > 1 &&
- templ->height0 % 4 == 1)
- info->qpitch += 4;
- }
- else {
- info->qpitch = h0;
- }
+ if (imported_bo) {
+ ilo_vma_set_bo(&tex->vma, &is->dev, imported_bo, 0);
+ tex->imported = true;
}
-}
-
-/**
- * Layout a 2D texture.
- */
-static void
-layout_tex_2d(struct ilo_resource *res, const struct layout_tex_info *info)
-{
- const struct pipe_resource *templ = &res->base;
- unsigned int level_x, level_y, num_slices;
- int lv;
-
- res->bo_width = 0;
- res->bo_height = 0;
-
- level_x = 0;
- level_y = 0;
- for (lv = 0; lv <= templ->last_level; lv++) {
- const unsigned int level_w = info->sizes[lv].w;
- const unsigned int level_h = info->sizes[lv].h;
- int slice;
-
- for (slice = 0; slice < templ->array_size; slice++) {
- res->slice_offsets[lv][slice].x = level_x;
- /* slices are qpitch apart in Y-direction */
- res->slice_offsets[lv][slice].y = level_y + info->qpitch * slice;
- }
- /* extend the size of the monolithic bo to cover this mip level */
- if (res->bo_width < level_x + level_w)
- res->bo_width = level_x + level_w;
- if (res->bo_height < level_y + level_h)
- res->bo_height = level_y + level_h;
-
- /* MIPLAYOUT_BELOW */
- if (lv == 1)
- level_x += align(level_w, info->align_i);
- else
- level_y += align(level_h, info->align_j);
+ if (templ->flags & PIPE_RESOURCE_FLAG_MAP_PERSISTENT) {
+ /* require on-the-fly tiling/untiling or format conversion */
+ if (img->tiling == GEN8_TILING_W || *separate_stencil ||
+ image_format != templ->format)
+ return false;
}
- num_slices = templ->array_size;
- /* samples of the same index are stored in a slice */
- if (templ->nr_samples > 1 && !info->interleaved)
- num_slices *= templ->nr_samples;
-
- /* we did not take slices into consideration in the computation above */
- res->bo_height += info->qpitch * (num_slices - 1);
-}
-
-/**
- * Layout a 3D texture.
- */
-static void
-layout_tex_3d(struct ilo_resource *res, const struct layout_tex_info *info)
-{
- const struct pipe_resource *templ = &res->base;
- unsigned int level_y;
- int lv;
-
- res->bo_width = 0;
- res->bo_height = 0;
-
- level_y = 0;
- for (lv = 0; lv <= templ->last_level; lv++) {
- const unsigned int level_w = info->sizes[lv].w;
- const unsigned int level_h = info->sizes[lv].h;
- const unsigned int level_d = info->sizes[lv].d;
- const unsigned int slice_pitch = align(level_w, info->align_i);
- const unsigned int slice_qpitch = align(level_h, info->align_j);
- const unsigned int num_slices_per_row = 1 << lv;
- int slice;
-
- for (slice = 0; slice < level_d; slice += num_slices_per_row) {
- int i;
-
- for (i = 0; i < num_slices_per_row && slice + i < level_d; i++) {
- res->slice_offsets[lv][slice + i].x = slice_pitch * i;
- res->slice_offsets[lv][slice + i].y = level_y;
- }
-
- /* move on to the next slice row */
- level_y += slice_qpitch;
- }
-
- /* rightmost slice */
- slice = MIN2(num_slices_per_row, level_d) - 1;
+ if (!tex_alloc_slices(tex))
+ return false;
- /* extend the size of the monolithic bo to cover this slice */
- if (res->bo_width < slice_pitch * slice + level_w)
- res->bo_width = slice_pitch * slice + level_w;
- if (lv == templ->last_level)
- res->bo_height = (level_y - slice_qpitch) + level_h;
- }
+ return true;
}
-/**
- * Guess the texture size. For large textures, the errors are relative small.
- */
-static size_t
-guess_tex_size(const struct pipe_resource *templ,
- enum intel_tiling_mode tiling)
+static struct pipe_resource *
+tex_create(struct pipe_screen *screen,
+ const struct pipe_resource *templ,
+ const struct winsys_handle *handle)
{
- int bo_width, bo_height, bo_stride;
+ struct ilo_texture *tex;
+ bool separate_stencil;
- /* HALIGN_8 and VALIGN_4 */
- bo_width = align(templ->width0, 8);
- bo_height = align(templ->height0, 4);
-
- if (templ->target == PIPE_TEXTURE_3D) {
- const int num_rows = util_next_power_of_two(templ->depth0);
- int lv, sum;
+ tex = CALLOC_STRUCT(ilo_texture);
+ if (!tex)
+ return NULL;
- sum = bo_height * templ->depth0;
- for (lv = 1; lv <= templ->last_level; lv++)
- sum += u_minify(bo_height, lv) * u_minify(num_rows, lv);
+ tex->base = *templ;
+ tex->base.screen = screen;
+ pipe_reference_init(&tex->base.reference, 1);
- bo_height = sum;
- }
- else if (templ->last_level > 0) {
- /* MIPLAYOUT_BELOW, ignore qpich */
- bo_height = (bo_height + u_minify(bo_height, 1)) * templ->array_size;
+ if (!tex_init_image(tex, handle, &separate_stencil)) {
+ FREE(tex);
+ return NULL;
}
- bo_stride = util_format_get_stride(templ->format, bo_width);
-
- switch (tiling) {
- case INTEL_TILING_X:
- bo_stride = align(bo_stride, 512);
- bo_height = align(bo_height, 8);
- break;
- case INTEL_TILING_Y:
- bo_stride = align(bo_stride, 128);
- bo_height = align(bo_height, 32);
- break;
- default:
- bo_height = align(bo_height, 2);
- break;
+ if (!tex_alloc_bos(tex) ||
+ (separate_stencil && !tex_create_separate_stencil(tex))) {
+ tex_destroy(tex);
+ return NULL;
}
- return util_format_get_2d_size(templ->format, bo_stride, bo_height);
+ return &tex->base;
}
-static enum intel_tiling_mode
-get_tex_tiling(const struct ilo_resource *res)
+static bool
+tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle)
{
- const struct pipe_resource *templ = &res->base;
- const enum pipe_format bo_format = res->bo_format;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "Display/Overlay Y-Major not supported.
- * X-Major required for Async Flips"
- */
- if (unlikely(templ->bind & PIPE_BIND_SCANOUT))
- return INTEL_TILING_X;
-
- /*
- * From the Sandy Bridge PRM, volume 3 part 2, page 158:
- *
- * "The cursor surface address must be 4K byte aligned. The cursor must
- * be in linear memory, it cannot be tiled."
- */
- if (unlikely(templ->bind & PIPE_BIND_CURSOR))
- return INTEL_TILING_NONE;
-
- /*
- * From the Ivy Bridge PRM, volume 4 part 1, page 76:
- *
- * "The MCS surface must be stored as Tile Y."
- */
- if (templ->bind & ILO_BIND_MCS)
- return INTEL_TILING_Y;
-
- /*
- * From the Sandy Bridge PRM, volume 2 part 1, page 318:
- *
- * "[DevSNB+]: This field (Tiled Surface) must be set to TRUE. Linear
- * Depth Buffer is not supported."
- *
- * "The Depth Buffer, if tiled, must use Y-Major tiling."
- */
- if (templ->bind & PIPE_BIND_DEPTH_STENCIL) {
- /* separate stencil uses W-tiling but we do not know how to specify that */
- return (bo_format == PIPE_FORMAT_S8_UINT) ?
- INTEL_TILING_NONE : INTEL_TILING_Y;
- }
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
+ enum intel_tiling_mode tiling;
+ int err;
- if (templ->bind & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_SAMPLER_VIEW)) {
- enum intel_tiling_mode tiling = INTEL_TILING_NONE;
-
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 32:
- *
- * "NOTE: 128BPE Format Color buffer ( render target ) MUST be
- * either TileX or Linear."
- *
- * Also, heuristically set a minimum width/height for enabling tiling.
- */
- if (util_format_get_blocksizebits(bo_format) == 128 &&
- (templ->bind & PIPE_BIND_RENDER_TARGET) && templ->width0 >= 64)
- tiling = INTEL_TILING_X;
- else if ((templ->width0 >= 32 && templ->height0 >= 16) ||
- (templ->width0 >= 16 && templ->height0 >= 32))
- tiling = INTEL_TILING_Y;
-
- /* make sure the bo can be mapped through GTT if tiled */
- if (tiling != INTEL_TILING_NONE) {
- /*
- * Usually only the first 256MB of the GTT is mappable.
- *
- * See also how intel_context::max_gtt_map_object_size is calculated.
- */
- const size_t mappable_gtt_size = 256 * 1024 * 1024;
- const size_t size = guess_tex_size(templ, tiling);
-
- /* be conservative */
- if (size > mappable_gtt_size / 4)
- tiling = INTEL_TILING_NONE;
- }
+ /* must match what tex_create_bo() sets */
+ if (tex->image.tiling == GEN8_TILING_W)
+ tiling = INTEL_TILING_NONE;
+ else
+ tiling = surface_to_winsys_tiling(tex->image.tiling);
- return tiling;
- }
+ err = intel_winsys_export_handle(is->dev.winsys, tex->vma.bo, tiling,
+ tex->image.bo_stride, tex->image.bo_height, handle);
- return INTEL_TILING_NONE;
+ return !err;
}
-static void
-init_texture(struct ilo_resource *res)
+static bool
+buf_create_bo(struct ilo_buffer_resource *buf)
{
- struct layout_tex_info info;
-
- switch (res->base.format) {
- case PIPE_FORMAT_ETC1_RGB8:
- res->bo_format = PIPE_FORMAT_R8G8B8X8_UNORM;
- break;
- default:
- res->bo_format = res->base.format;
- break;
- }
-
- /* determine tiling first as it may affect the layout */
- res->tiling = get_tex_tiling(res);
-
- layout_tex_init(res, &info);
-
- res->compressed = info.compressed;
- res->block_width = info.block_width;
- res->block_height = info.block_height;
-
- res->halign_8 = (info.align_i == 8);
- res->valign_4 = (info.align_j == 4);
- res->array_spacing_full = info.array_spacing_full;
- res->interleaved = info.interleaved;
+ struct ilo_screen *is = ilo_screen(buf->base.screen);
+ const char *name = resource_get_bo_name(&buf->base);
+ const bool cpu_init = resource_get_cpu_init(&buf->base);
+ struct intel_bo *bo;
- switch (res->base.target) {
- case PIPE_TEXTURE_1D:
- case PIPE_TEXTURE_2D:
- case PIPE_TEXTURE_CUBE:
- case PIPE_TEXTURE_RECT:
- case PIPE_TEXTURE_1D_ARRAY:
- case PIPE_TEXTURE_2D_ARRAY:
- case PIPE_TEXTURE_CUBE_ARRAY:
- layout_tex_2d(res, &info);
- break;
- case PIPE_TEXTURE_3D:
- layout_tex_3d(res, &info);
- break;
- default:
- assert(!"unknown resource target");
- break;
- }
+ bo = intel_winsys_alloc_bo(is->dev.winsys, name, buf->bo_size, cpu_init);
+ if (!bo)
+ return false;
- /*
- * From the Sandy Bridge PRM, volume 1 part 2, page 22:
- *
- * "A 4KB tile is subdivided into 8-high by 8-wide array of Blocks for
- * W-Major Tiles (W Tiles). Each Block is 8 rows by 8 bytes."
- *
- * Since we ask for INTEL_TILING_NONE instead lf INTEL_TILING_W, we need to
- * manually align the bo width and height to the tile boundaries.
- */
- if (res->bo_format == PIPE_FORMAT_S8_UINT) {
- res->bo_width = align(res->bo_width, 64);
- res->bo_height = align(res->bo_height, 64);
- }
+ intel_bo_unref(buf->vma.bo);
+ ilo_vma_set_bo(&buf->vma, &is->dev, bo, 0);
- /* in blocks */
- assert(res->bo_width % info.block_width == 0);
- assert(res->bo_height % info.block_height == 0);
- res->bo_width /= info.block_width;
- res->bo_height /= info.block_height;
- res->bo_cpp = util_format_get_blocksize(res->bo_format);
+ return true;
}
static void
-init_buffer(struct ilo_resource *res)
+buf_destroy(struct ilo_buffer_resource *buf)
{
- res->bo_format = res->base.format;
- res->bo_width = res->base.width0;
- res->bo_height = 1;
- res->bo_cpp = 1;
- res->bo_stride = 0;
- res->tiling = INTEL_TILING_NONE;
-
- res->compressed = false;
- res->block_width = 1;
- res->block_height = 1;
-
- res->halign_8 = false;
- res->valign_4 = false;
- res->array_spacing_full = false;
- res->interleaved = false;
+ intel_bo_unref(buf->vma.bo);
+ FREE(buf);
}
static struct pipe_resource *
-create_resource(struct pipe_screen *screen,
- const struct pipe_resource *templ,
- struct winsys_handle *handle)
+buf_create(struct pipe_screen *screen, const struct pipe_resource *templ)
{
- struct ilo_resource *res;
+ const struct ilo_screen *is = ilo_screen(screen);
+ struct ilo_buffer_resource *buf;
+ uint32_t alignment;
+ unsigned size;
- res = CALLOC_STRUCT(ilo_resource);
- if (!res)
+ buf = CALLOC_STRUCT(ilo_buffer_resource);
+ if (!buf)
return NULL;
- res->base = *templ;
- res->base.screen = screen;
- pipe_reference_init(&res->base.reference, 1);
- res->handle = handle;
+ buf->base = *templ;
+ buf->base.screen = screen;
+ pipe_reference_init(&buf->base.reference, 1);
- if (!alloc_slice_offsets(res)) {
- FREE(res);
- return NULL;
- }
+ size = templ->width0;
- if (templ->target == PIPE_BUFFER)
- init_buffer(res);
- else
- init_texture(res);
-
- if (!realloc_bo(res)) {
- free_slice_offsets(res);
- FREE(res);
+ /*
+ * As noted in ilo_format_translate(), we treat some 3-component formats as
+ * 4-component formats to work around hardware limitations. Imagine the
+ * case where the vertex buffer holds a single PIPE_FORMAT_R16G16B16_FLOAT
+ * vertex, and buf->bo_size is 6. The hardware would fail to fetch it at
+ * boundary check because the vertex buffer is expected to hold a
+ * PIPE_FORMAT_R16G16B16A16_FLOAT vertex and that takes at least 8 bytes.
+ *
+ * For the workaround to work, we should add 2 to the bo size. But that
+ * would waste a page when the bo size is already page aligned. Let's
+ * round it to page size for now and revisit this when needed.
+ */
+ if ((templ->bind & PIPE_BIND_VERTEX_BUFFER) &&
+ ilo_dev_gen(&is->dev) < ILO_GEN(7.5))
+ size = align(size, 4096);
+
+ if (templ->bind & PIPE_BIND_VERTEX_BUFFER)
+ size = ilo_state_vertex_buffer_size(&is->dev, size, &alignment);
+ if (templ->bind & PIPE_BIND_INDEX_BUFFER)
+ size = ilo_state_index_buffer_size(&is->dev, size, &alignment);
+ if (templ->bind & PIPE_BIND_STREAM_OUTPUT)
+ size = ilo_state_sol_buffer_size(&is->dev, size, &alignment);
+
+ buf->bo_size = size;
+ ilo_vma_init(&buf->vma, &is->dev, buf->bo_size, 4096);
+
+ if (buf->bo_size < templ->width0 || buf->bo_size > ilo_max_resource_size ||
+ !buf_create_bo(buf)) {
+ FREE(buf);
return NULL;
}
- return &res->base;
+ return &buf->base;
}
static boolean
ilo_can_create_resource(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
- /*
- * We do not know if we will fail until we try to allocate the bo.
- * So just set a limit on the texture size.
- */
- const size_t max_size = 1 * 1024 * 1024 * 1024;
- const size_t size = guess_tex_size(templ, INTEL_TILING_Y);
+ struct ilo_screen *is = ilo_screen(screen);
+ enum pipe_format image_format;
+ struct ilo_image_info info;
+ struct ilo_image img;
+
+ if (templ->target == PIPE_BUFFER)
+ return (templ->width0 <= ilo_max_resource_size);
+
+ image_format = resource_get_image_format(templ, &is->dev, NULL);
+ resource_get_image_info(templ, &is->dev, image_format, &info);
+
+ memset(&img, 0, sizeof(img));
+ ilo_image_init(&img, &ilo_screen(screen)->dev, &info);
+
+ /* as in tex_init_image() */
+ if (ilo_dev_gen(&is->dev) == ILO_GEN(6) &&
+ templ->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT &&
+ image_format == PIPE_FORMAT_Z32_FLOAT &&
+ img.aux.enables != (1 << templ->last_level)) {
+ info.format = templ->format;
+ memset(&img, 0, sizeof(img));
+ ilo_image_init(&img, &ilo_screen(screen)->dev, &info);
+ }
- return (size <= max_size);
+ return (img.bo_height <= ilo_max_resource_size / img.bo_stride);
}
static struct pipe_resource *
ilo_resource_create(struct pipe_screen *screen,
const struct pipe_resource *templ)
{
- return create_resource(screen, templ, NULL);
+ if (templ->target == PIPE_BUFFER)
+ return buf_create(screen, templ);
+ else
+ return tex_create(screen, templ, NULL);
}
static struct pipe_resource *
const struct pipe_resource *templ,
struct winsys_handle *handle)
{
- return create_resource(screen, templ, handle);
+ if (templ->target == PIPE_BUFFER)
+ return NULL;
+ else
+ return tex_create(screen, templ, handle);
}
static boolean
ilo_resource_get_handle(struct pipe_screen *screen,
- struct pipe_resource *r,
+ struct pipe_resource *res,
struct winsys_handle *handle)
{
- struct ilo_resource *res = ilo_resource(r);
- int err;
-
- err = res->bo->export_handle(res->bo, handle);
+ if (res->target == PIPE_BUFFER)
+ return false;
+ else
+ return tex_get_handle(ilo_texture(res), handle);
- return !err;
}
static void
ilo_resource_destroy(struct pipe_screen *screen,
- struct pipe_resource *r)
+ struct pipe_resource *res)
{
- struct ilo_resource *res = ilo_resource(r);
-
- free_slice_offsets(res);
- res->bo->unreference(res->bo);
- FREE(res);
+ if (res->target == PIPE_BUFFER)
+ buf_destroy((struct ilo_buffer_resource *) res);
+ else
+ tex_destroy(ilo_texture(res));
}
/**
is->base.resource_destroy = ilo_resource_destroy;
}
-/**
- * Initialize transfer-related functions.
- */
-void
-ilo_init_transfer_functions(struct ilo_context *ilo)
+bool
+ilo_resource_rename_bo(struct pipe_resource *res)
{
- ilo->base.transfer_map = ilo_transfer_map;
- ilo->base.transfer_flush_region = ilo_transfer_flush_region;
- ilo->base.transfer_unmap = ilo_transfer_unmap;
- ilo->base.transfer_inline_write = ilo_transfer_inline_write;
-}
+ if (res->target == PIPE_BUFFER) {
+ return buf_create_bo((struct ilo_buffer_resource *) res);
+ } else {
+ struct ilo_texture *tex = ilo_texture(res);
-/**
- * Return the offset (in bytes) to a slice within the bo.
- *
- * When tile_aligned is true, the offset is to the tile containing the start
- * address of the slice. x_offset and y_offset are offsets (in pixels) from
- * the tile start to slice start. x_offset is always a multiple of 4 and
- * y_offset is always a multiple of 2.
- */
-unsigned
-ilo_resource_get_slice_offset(const struct ilo_resource *res,
- int level, int slice, bool tile_aligned,
- unsigned *x_offset, unsigned *y_offset)
-{
- const unsigned x = res->slice_offsets[level][slice].x / res->block_width;
- const unsigned y = res->slice_offsets[level][slice].y / res->block_height;
- unsigned tile_w, tile_h, tile_size, row_size;
- unsigned slice_offset;
-
- /* see the Sandy Bridge PRM, volume 1 part 2, page 24 */
-
- switch (res->tiling) {
- case INTEL_TILING_NONE:
- tile_w = res->bo_cpp;
- tile_h = 1;
- break;
- case INTEL_TILING_X:
- tile_w = 512;
- tile_h = 8;
- break;
- case INTEL_TILING_Y:
- tile_w = 128;
- tile_h = 32;
- break;
- default:
- assert(!"unknown tiling");
- tile_w = res->bo_cpp;
- tile_h = 1;
- break;
- }
-
- tile_size = tile_w * tile_h;
- row_size = res->bo_stride * tile_h;
-
- /*
- * for non-tiled resources, this is equivalent to
- *
- * slice_offset = y * res->bo_stride + x * res->bo_cpp;
- */
- slice_offset =
- row_size * (y / tile_h) + tile_size * (x * res->bo_cpp / tile_w);
-
- /*
- * Since res->bo_stride is a multiple of tile_w, slice_offset should be
- * aligned at this point.
- */
- assert(slice_offset % tile_size == 0);
-
- if (tile_aligned) {
- /*
- * because of the possible values of align_i and align_j in
- * layout_tex_init(), x_offset must be a multiple of 4 and y_offset must
- * be a multiple of 2.
- */
- if (x_offset) {
- assert(tile_w % res->bo_cpp == 0);
- *x_offset = (x % (tile_w / res->bo_cpp)) * res->block_width;
- assert(*x_offset % 4 == 0);
- }
- if (y_offset) {
- *y_offset = (y % tile_h) * res->block_height;
- assert(*y_offset % 2 == 0);
- }
- }
- else {
- const unsigned tx = (x * res->bo_cpp) % tile_w;
- const unsigned ty = y % tile_h;
-
- switch (res->tiling) {
- case INTEL_TILING_NONE:
- assert(tx == 0 && ty == 0);
- break;
- case INTEL_TILING_X:
- slice_offset += tile_w * ty + tx;
- break;
- case INTEL_TILING_Y:
- slice_offset += tile_h * 16 * (tx / 16) + ty * 16 + (tx % 16);
- break;
- }
+ /* an imported texture cannot be renamed */
+ if (tex->imported)
+ return false;
- if (x_offset)
- *x_offset = 0;
- if (y_offset)
- *y_offset = 0;
+ return tex_create_bo(tex);
}
-
- return slice_offset;
}
projects / mesa.git / blobdiff