ilo: add BLT-based blitting methods to ilo_blitter

[mesa.git] / src / gallium / drivers / ilo / ilo_screen.c

diff --git a/src/gallium/drivers/ilo/ilo_screen.c b/src/gallium/drivers/ilo/ilo_screen.c
index 361320421566bbad4963b0a2faeb7a7dc8e9027b..d2b211366b10e09b1038ccbf16b3a5c5d30c5cdd 100644 (file)
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -132,7 +132,7 @@ ilo_get_shader_param(struct pipe_screen *screen, unsigned shader,
    case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
       return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
    case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
-      return (shader == PIPE_SHADER_FRAGMENT) ? 0 : 1;
+      return 1;
    case PIPE_SHADER_CAP_SUBROUTINES:
       return 0;
    case PIPE_SHADER_CAP_INTEGERS:
@@ -347,7 +347,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return false;
    case PIPE_CAP_TGSI_INSTANCEID:
    case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
-      return false; /* TODO */
+      return true;
    case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
       return false;
    case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
@@ -380,7 +380,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_VERTEX_COLOR_CLAMPED:
       return false;
    case PIPE_CAP_GLSL_FEATURE_LEVEL:
-      return 130;
+      return 140;
    case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
    case PIPE_CAP_USER_VERTEX_BUFFERS:
       return false;
@@ -395,6 +395,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_USER_CONSTANT_BUFFERS:
       return false; /* TODO push constants */
    case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
+      /* imposed by OWord (Dual) Block Read */
       return 16;
    case PIPE_CAP_START_INSTANCE:
    case PIPE_CAP_QUERY_TIMESTAMP:
@@ -402,12 +403,12 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_MULTISAMPLE:
       return false; /* TODO */
    case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
-      return 0; /* TODO */
+      return 0;
    case PIPE_CAP_CUBE_MAP_ARRAY:
    case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
-      return false; /* TODO */
+      return true;
    case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
-      return 0; /* TODO */
+      return 1;
    case PIPE_CAP_TGSI_TEXCOORD:
       return false;
    case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
@@ -416,6 +417,11 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap param)
       return false; /* TODO */
    case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
       return 0;
+   case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
+      /* a BRW_SURFACE_BUFFER can have up to 2^27 elements */
+      return 1 << 27;
+   case PIPE_CAP_MAX_VIEWPORTS:
+      return ILO_MAX_VIEWPORTS;
 
    default:
       return 0;
@@ -470,44 +476,44 @@ ilo_get_name(struct pipe_screen *screen)
       break;
    case PCI_CHIP_HASWELL_GT1:
    case PCI_CHIP_HASWELL_GT2:
-   case PCI_CHIP_HASWELL_GT2_PLUS:
+   case PCI_CHIP_HASWELL_GT3:
    case PCI_CHIP_HASWELL_SDV_GT1:
    case PCI_CHIP_HASWELL_SDV_GT2:
-   case PCI_CHIP_HASWELL_SDV_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_GT3:
    case PCI_CHIP_HASWELL_ULT_GT1:
    case PCI_CHIP_HASWELL_ULT_GT2:
-   case PCI_CHIP_HASWELL_ULT_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_GT3:
    case PCI_CHIP_HASWELL_CRW_GT1:
    case PCI_CHIP_HASWELL_CRW_GT2:
-   case PCI_CHIP_HASWELL_CRW_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_GT3:
       chipset = "Intel(R) Haswell Desktop";
       break;
    case PCI_CHIP_HASWELL_M_GT1:
    case PCI_CHIP_HASWELL_M_GT2:
-   case PCI_CHIP_HASWELL_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_M_GT3:
    case PCI_CHIP_HASWELL_SDV_M_GT1:
    case PCI_CHIP_HASWELL_SDV_M_GT2:
-   case PCI_CHIP_HASWELL_SDV_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_M_GT3:
    case PCI_CHIP_HASWELL_ULT_M_GT1:
    case PCI_CHIP_HASWELL_ULT_M_GT2:
-   case PCI_CHIP_HASWELL_ULT_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_M_GT3:
    case PCI_CHIP_HASWELL_CRW_M_GT1:
    case PCI_CHIP_HASWELL_CRW_M_GT2:
-   case PCI_CHIP_HASWELL_CRW_M_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_M_GT3:
       chipset = "Intel(R) Haswell Mobile";
       break;
    case PCI_CHIP_HASWELL_S_GT1:
    case PCI_CHIP_HASWELL_S_GT2:
-   case PCI_CHIP_HASWELL_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_S_GT3:
    case PCI_CHIP_HASWELL_SDV_S_GT1:
    case PCI_CHIP_HASWELL_SDV_S_GT2:
-   case PCI_CHIP_HASWELL_SDV_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_SDV_S_GT3:
    case PCI_CHIP_HASWELL_ULT_S_GT1:
    case PCI_CHIP_HASWELL_ULT_S_GT2:
-   case PCI_CHIP_HASWELL_ULT_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_ULT_S_GT3:
    case PCI_CHIP_HASWELL_CRW_S_GT1:
    case PCI_CHIP_HASWELL_CRW_S_GT2:
-   case PCI_CHIP_HASWELL_CRW_S_GT2_PLUS:
+   case PCI_CHIP_HASWELL_CRW_S_GT3:
       chipset = "Intel(R) Haswell Server";
       break;
    default:
@@ -527,7 +533,7 @@ ilo_get_timestamp(struct pipe_screen *screen)
       uint32_t dw[2];
    } timestamp;
 
-   is->winsys->read_reg(is->winsys, TIMESTAMP, &timestamp.val);
+   intel_winsys_read_reg(is->winsys, TIMESTAMP, &timestamp.val);
 
    /*
     * From the Ivy Bridge PRM, volume 1 part 3, page 107:
@@ -566,7 +572,7 @@ ilo_fence_reference(struct pipe_screen *screen,
       struct ilo_fence *old = *ptr;
 
       if (old->bo)
-         old->bo->unreference(old->bo);
+         intel_bo_unreference(old->bo);
       FREE(old);
    }
 
@@ -581,7 +587,7 @@ ilo_fence_signalled(struct pipe_screen *screen,
 
    /* mark signalled if the bo is idle */
    if (fence->bo && !intel_bo_is_busy(fence->bo)) {
-      fence->bo->unreference(fence->bo);
+      intel_bo_unreference(fence->bo);
       fence->bo = NULL;
    }
 
@@ -601,11 +607,11 @@ ilo_fence_finish(struct pipe_screen *screen,
       return true;
 
    /* wait and see if it returns error */
-   if (fence->bo->wait(fence->bo, wait_timeout))
+   if (intel_bo_wait(fence->bo, wait_timeout))
       return false;
 
    /* mark signalled */
-   fence->bo->unreference(fence->bo);
+   intel_bo_unreference(fence->bo);
    fence->bo = NULL;
 
    return true;
@@ -617,7 +623,7 @@ ilo_screen_destroy(struct pipe_screen *screen)
    struct ilo_screen *is = ilo_screen(screen);
 
    /* as it seems, winsys is owned by the screen */
-   is->winsys->destroy(is->winsys);
+   intel_winsys_destroy(is->winsys);
 
    FREE(is);
 }
@@ -649,13 +655,17 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
    if (IS_HASWELL(info->devid)) {
       dev->gen = ILO_GEN(7.5);
 
-      if (IS_HSW_GT2(info->devid)) {
+      if (IS_HSW_GT3(info->devid)) {
+         dev->gt = 3;
+         dev->urb_size = 512 * 1024;
+      }
+      else if (IS_HSW_GT2(info->devid)) {
          dev->gt = 2;
-        dev->urb_size = 256 * 1024;
+         dev->urb_size = 256 * 1024;
       }
       else {
          dev->gt = 1;
-        dev->urb_size = 128 * 1024;
+         dev->urb_size = 128 * 1024;
       }
    }
    else if (IS_GEN7(info->devid)) {
@@ -663,11 +673,11 @@ init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
 
       if (IS_IVB_GT2(info->devid)) {
          dev->gt = 2;
-        dev->urb_size = 256 * 1024;
+         dev->urb_size = 256 * 1024;
       }
       else {
          dev->gt = 1;
-        dev->urb_size = 128 * 1024;
+         dev->urb_size = 128 * 1024;
       }
    }
    else if (IS_GEN6(info->devid)) {
@@ -704,7 +714,9 @@ ilo_screen_create(struct intel_winsys *ws)
 
    is->winsys = ws;
 
-   info = is->winsys->get_info(is->winsys);
+   intel_winsys_enable_reuse(is->winsys);
+
+   info = intel_winsys_get_info(is->winsys);
    if (!init_dev(&is->dev, info)) {
       FREE(is);
       return NULL;