#include "drm-uapi/i915_drm.h"
+#include "intel/common/gen_gem.h"
#include "util/hash_table.h"
#include "util/set.h"
#include "main/macros.h"
#include <errno.h>
#include <xf86drm.h>
+#if HAVE_VALGRIND
+#include <valgrind.h>
+#include <memcheck.h>
+#define VG(x) x
+#else
+#define VG(x)
+#endif
+
#define FILE_DEBUG_FLAG DEBUG_BUFMGR
/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
* Return BO information to the batch decoder (for debugging).
*/
static struct gen_batch_decode_bo
-decode_get_bo(void *v_batch, uint64_t address)
+decode_get_bo(void *v_batch, bool ppgtt, uint64_t address)
{
struct iris_batch *batch = v_batch;
+ assert(ppgtt);
+
for (int i = 0; i < batch->exec_count; i++) {
struct iris_bo *bo = batch->exec_bos[i];
/* The decoder zeroes out the top 16 bits, so we need to as well */
return (struct gen_batch_decode_bo) { };
}
+static unsigned
+decode_get_state_size(void *v_batch, uint32_t offset_from_base)
+{
+ struct iris_batch *batch = v_batch;
+
+ /* The decoder gives us offsets from a base address, which is not great.
+ * Binding tables are relative to surface state base address, and other
+ * state is relative to dynamic state base address. These could alias,
+ * but in practice it's unlikely because surface offsets are always in
+ * the [0, 64K) range, and we assign dynamic state addresses starting at
+ * the top of the 4GB range. We should fix this but it's likely good
+ * enough for now.
+ */
+ unsigned size = (uintptr_t)
+ _mesa_hash_table_u64_search(batch->state_sizes, offset_from_base);
+
+ return size;
+}
+
/**
* Decode the current batch.
*/
{
void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
gen_print_batch(&batch->decoder, map, batch->primary_batch_size,
- batch->exec_bos[0]->gtt_offset);
-}
-
-static bool
-uint_key_compare(const void *a, const void *b)
-{
- return a == b;
-}
-
-static uint32_t
-uint_key_hash(const void *key)
-{
- return (uintptr_t) key;
+ batch->exec_bos[0]->gtt_offset, false);
}
void
struct iris_screen *screen,
struct iris_vtable *vtbl,
struct pipe_debug_callback *dbg,
+ struct pipe_device_reset_callback *reset,
+ struct hash_table_u64 *state_sizes,
struct iris_batch *all_batches,
enum iris_batch_name name,
- uint8_t engine)
+ uint8_t engine,
+ int priority)
{
batch->screen = screen;
batch->vtbl = vtbl;
batch->dbg = dbg;
+ batch->reset = reset;
+ batch->state_sizes = state_sizes;
batch->name = name;
/* engine should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
assert(batch->hw_ctx_id);
+ iris_hw_context_set_priority(screen->bufmgr, batch->hw_ctx_id, priority);
+
util_dynarray_init(&batch->exec_fences, ralloc_context(NULL));
util_dynarray_init(&batch->syncpts, ralloc_context(NULL));
}
if (unlikely(INTEL_DEBUG)) {
- batch->state_sizes =
- _mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);
-
const unsigned decode_flags =
GEN_BATCH_DECODE_FULL |
((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
gen_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
stderr, decode_flags, NULL,
- decode_get_bo, NULL, batch);
+ decode_get_bo, decode_get_state_size, batch);
+ batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START;
+ batch->decoder.instruction_base = IRIS_MEMZONE_SHADER_START;
batch->decoder.max_vbo_decoded_lines = 32;
}
iris_batch_reset(batch);
}
-#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
-
static struct drm_i915_gem_exec_object2 *
find_validation_entry(struct iris_batch *batch, struct iris_bo *bo)
{
return;
}
- /* This is the first time our batch has seen this BO. Before we use it,
- * we may need to flush and synchronize with other batches.
- */
- for (int b = 0; b < ARRAY_SIZE(batch->other_batches); b++) {
- struct drm_i915_gem_exec_object2 *other_entry =
- find_validation_entry(batch->other_batches[b], bo);
-
- /* If the buffer is referenced by another batch, and either batch
- * intends to write it, then flush the other batch and synchronize.
- *
- * Consider these cases:
- *
- * 1. They read, we read => No synchronization required.
- * 2. They read, we write => Synchronize (they need the old value)
- * 3. They write, we read => Synchronize (we need their new value)
- * 4. They write, we write => Synchronize (order writes)
- *
- * The read/read case is very common, as multiple batches usually
- * share a streaming state buffer or shader assembly buffer, and
- * we want to avoid synchronizing in this case.
+ if (bo != batch->bo) {
+ /* This is the first time our batch has seen this BO. Before we use it,
+ * we may need to flush and synchronize with other batches.
*/
- if (other_entry &&
- ((other_entry->flags & EXEC_OBJECT_WRITE) || writable)) {
- iris_batch_flush(batch->other_batches[b]);
- iris_batch_add_syncpt(batch, batch->other_batches[b]->last_syncpt,
- I915_EXEC_FENCE_WAIT);
+ for (int b = 0; b < ARRAY_SIZE(batch->other_batches); b++) {
+ struct drm_i915_gem_exec_object2 *other_entry =
+ find_validation_entry(batch->other_batches[b], bo);
+
+ /* If the buffer is referenced by another batch, and either batch
+ * intends to write it, then flush the other batch and synchronize.
+ *
+ * Consider these cases:
+ *
+ * 1. They read, we read => No synchronization required.
+ * 2. They read, we write => Synchronize (they need the old value)
+ * 3. They write, we read => Synchronize (we need their new value)
+ * 4. They write, we write => Synchronize (order writes)
+ *
+ * The read/read case is very common, as multiple batches usually
+ * share a streaming state buffer or shader assembly buffer, and
+ * we want to avoid synchronizing in this case.
+ */
+ if (other_entry &&
+ ((other_entry->flags & EXEC_OBJECT_WRITE) || writable)) {
+ iris_batch_flush(batch->other_batches[b]);
+ iris_batch_add_syncpt(batch, batch->other_batches[b]->last_syncpt,
+ I915_EXEC_FENCE_WAIT);
+ }
}
}
iris_bo_unreference(batch->bo);
batch->primary_batch_size = 0;
batch->contains_draw = false;
+ batch->decoder.surface_base = batch->last_surface_base_address;
create_batch(batch);
assert(batch->bo->index == 0);
iris_batch_add_syncpt(batch, syncpt, I915_EXEC_FENCE_SIGNAL);
iris_syncpt_reference(screen, &syncpt, NULL);
- if (batch->state_sizes)
- _mesa_hash_table_clear(batch->state_sizes, NULL);
-
iris_cache_sets_clear(batch);
}
_mesa_hash_table_destroy(batch->cache.render, NULL);
_mesa_set_destroy(batch->cache.depth, NULL);
- if (batch->state_sizes) {
- _mesa_hash_table_destroy(batch->state_sizes, NULL);
+ if (unlikely(INTEL_DEBUG))
gen_batch_decode_ctx_finish(&batch->decoder);
- }
}
/**
/* We only support chaining a single time. */
assert(batch->bo == batch->exec_bos[0]);
+ VG(void *map = batch->map);
uint32_t *cmd = batch->map_next;
uint64_t *addr = batch->map_next + 4;
- batch->map_next += 8;
+ batch->map_next += 12;
/* No longer held by batch->bo, still held by validation list */
iris_bo_unreference(batch->bo);
/* Emit MI_BATCH_BUFFER_START to chain to another batch. */
*cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
*addr = batch->bo->gtt_offset;
+
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(map, batch->primary_batch_size));
}
/**
static void
iris_finish_batch(struct iris_batch *batch)
{
- // XXX: ISP DIS
-
/* Emit MI_BATCH_BUFFER_END to finish our batch. */
uint32_t *map = batch->map_next;
map[0] = (0xA << 23);
batch->map_next += 4;
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch->map, iris_batch_bytes_used(batch)));
if (batch->bo == batch->exec_bos[0])
batch->primary_batch_size = iris_batch_bytes_used(batch);
}
+/**
+ * Replace our current GEM context with a new one (in case it got banned).
+ */
+static bool
+replace_hw_ctx(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ struct iris_bufmgr *bufmgr = screen->bufmgr;
+
+ uint32_t new_ctx = iris_clone_hw_context(bufmgr, batch->hw_ctx_id);
+ if (!new_ctx)
+ return false;
+
+ iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
+ batch->hw_ctx_id = new_ctx;
+
+ /* Notify the context that state must be re-initialized. */
+ iris_lost_context_state(batch);
+
+ return true;
+}
+
+enum pipe_reset_status
+iris_batch_check_for_reset(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ enum pipe_reset_status status = PIPE_NO_RESET;
+ struct drm_i915_reset_stats stats = { .ctx_id = batch->hw_ctx_id };
+
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats))
+ DBG("DRM_IOCTL_I915_GET_RESET_STATS failed: %s\n", strerror(errno));
+
+ if (stats.batch_active != 0) {
+ /* A reset was observed while a batch from this hardware context was
+ * executing. Assume that this context was at fault.
+ */
+ status = PIPE_GUILTY_CONTEXT_RESET;
+ } else if (stats.batch_pending != 0) {
+ /* A reset was observed while a batch from this context was in progress,
+ * but the batch was not executing. In this case, assume that the
+ * context was not at fault.
+ */
+ status = PIPE_INNOCENT_CONTEXT_RESET;
+ }
+
+ if (status != PIPE_NO_RESET) {
+ /* Our context is likely banned, or at least in an unknown state.
+ * Throw it away and start with a fresh context. Ideally this may
+ * catch the problem before our next execbuf fails with -EIO.
+ */
+ replace_hw_ctx(batch);
+ }
+
+ return status;
+}
+
/**
* Submit the batch to the GPU via execbuffer2.
*/
(uintptr_t)util_dynarray_begin(&batch->exec_fences);
}
- int ret = drm_ioctl(batch->screen->fd,
- DRM_IOCTL_I915_GEM_EXECBUFFER2,
- &execbuf);
- if (ret != 0) {
+ int ret = 0;
+ if (!batch->screen->no_hw &&
+ gen_ioctl(batch->screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf))
ret = -errno;
- DBG("execbuf FAILED: errno = %d\n", -ret);
- fprintf(stderr, "execbuf FAILED: errno = %d\n", -ret);
- abort();
- } else {
- DBG("execbuf succeeded\n");
- }
for (int i = 0; i < batch->exec_count; i++) {
struct iris_bo *bo = batch->exec_bos[i];
iris_finish_batch(batch);
- if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
+ if (unlikely(INTEL_DEBUG &
+ (DEBUG_BATCH | DEBUG_SUBMIT | DEBUG_PIPE_CONTROL))) {
int bytes_for_commands = iris_batch_bytes_used(batch);
int second_bytes = 0;
if (batch->bo != batch->exec_bos[0]) {
100.0f * bytes_for_commands / BATCH_SZ,
batch->exec_count,
(float) batch->aperture_space / (1024 * 1024));
- dump_fence_list(batch);
- dump_validation_list(batch);
- }
-
- if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
- decode_batch(batch);
- }
-
- int ret = submit_batch(batch);
- if (ret >= 0) {
- //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
- //iris_check_for_reset(ice);
+ if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
+ dump_fence_list(batch);
+ dump_validation_list(batch);
+ }
- if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
- dbg_printf("waiting for idle\n");
- iris_bo_wait_rendering(batch->bo);
+ if (INTEL_DEBUG & DEBUG_BATCH) {
+ decode_batch(batch);
}
- } else {
-#ifdef DEBUG
- const bool color = INTEL_DEBUG & DEBUG_COLOR;
- fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
- color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
- abort();
-#endif
}
+ int ret = submit_batch(batch);
+
batch->exec_count = 0;
batch->aperture_space = 0;
util_dynarray_clear(&batch->exec_fences);
+ if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
+ dbg_printf("waiting for idle\n");
+ iris_bo_wait_rendering(batch->bo); /* if execbuf failed; this is a nop */
+ }
+
/* Start a new batch buffer. */
iris_batch_reset(batch);
+
+ /* EIO means our context is banned. In this case, try and replace it
+ * with a new logical context, and inform iris_context that all state
+ * has been lost and needs to be re-initialized. If this succeeds,
+ * dubiously claim success...
+ */
+ if (ret == -EIO && replace_hw_ctx(batch)) {
+ if (batch->reset->reset) {
+ /* Tell the state tracker the device is lost and it was our fault. */
+ batch->reset->reset(batch->reset->data, PIPE_GUILTY_CONTEXT_RESET);
+ }
+
+ ret = 0;
+ }
+
+ if (ret < 0) {
+#ifdef DEBUG
+ const bool color = INTEL_DEBUG & DEBUG_COLOR;
+ fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
+ color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
+#endif
+ abort();
+ }
}
/**