* Copyright © 2017 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * @file iris_batch.c
+ *
+ * Batchbuffer and command submission module.
+ *
+ * Every API draw call results in a number of GPU commands, which we
+ * collect into a "batch buffer". Typically, many draw calls are grouped
+ * into a single batch to amortize command submission overhead.
+ *
+ * We submit batches to the kernel using the I915_GEM_EXECBUFFER2 ioctl.
+ * One critical piece of data is the "validation list", which contains a
+ * list of the buffer objects (BOs) which the commands in the GPU need.
+ * The kernel will make sure these are resident and pinned at the correct
+ * virtual memory address before executing our batch. If a BO is not in
+ * the validation list, it effectively does not exist, so take care.
*/
#include "iris_batch.h"
-#include "iris_binder.h"
#include "iris_bufmgr.h"
#include "iris_context.h"
+#include "iris_fence.h"
#include "drm-uapi/i915_drm.h"
+#include "common/gen_aux_map.h"
+#include "intel/common/gen_gem.h"
#include "util/hash_table.h"
#include "util/set.h"
#include "main/macros.h"
#include <errno.h>
#include <xf86drm.h>
-#define FILE_DEBUG_FLAG DEBUG_BUFMGR
+#if HAVE_VALGRIND
+#include <valgrind.h>
+#include <memcheck.h>
+#define VG(x) x
+#else
+#define VG(x)
+#endif
-#define BATCH_SZ (20 * 1024)
+#define FILE_DEBUG_FLAG DEBUG_BUFMGR
/* Terminating the batch takes either 4 bytes for MI_BATCH_BUFFER_END
* or 12 bytes for MI_BATCH_BUFFER_START (when chaining). Plus, we may
*/
#define BATCH_RESERVED 16
-static void decode_batch(struct iris_batch *batch);
-
static void
iris_batch_reset(struct iris_batch *batch);
-UNUSED static void
+static unsigned
+num_fences(struct iris_batch *batch)
+{
+ return util_dynarray_num_elements(&batch->exec_fences,
+ struct drm_i915_gem_exec_fence);
+}
+
+/**
+ * Debugging code to dump the fence list, used by INTEL_DEBUG=submit.
+ */
+static void
+dump_fence_list(struct iris_batch *batch)
+{
+ fprintf(stderr, "Fence list (length %u): ", num_fences(batch));
+
+ util_dynarray_foreach(&batch->exec_fences,
+ struct drm_i915_gem_exec_fence, f) {
+ fprintf(stderr, "%s%u%s ",
+ (f->flags & I915_EXEC_FENCE_WAIT) ? "..." : "",
+ f->handle,
+ (f->flags & I915_EXEC_FENCE_SIGNAL) ? "!" : "");
+ }
+
+ fprintf(stderr, "\n");
+}
+
+/**
+ * Debugging code to dump the validation list, used by INTEL_DEBUG=submit.
+ */
+static void
dump_validation_list(struct iris_batch *batch)
{
fprintf(stderr, "Validation list (length %d):\n", batch->exec_count);
uint64_t flags = batch->validation_list[i].flags;
assert(batch->validation_list[i].handle ==
batch->exec_bos[i]->gem_handle);
- fprintf(stderr, "[%2d]: %2d %-14s %p %-7s @ 0x%016llx (%"PRIu64"B) - %d refs\n",
+ fprintf(stderr, "[%2d]: %2d %-14s @ 0x%016llx (%"PRIu64"B)\t %2d refs %s\n",
i,
batch->validation_list[i].handle,
batch->exec_bos[i]->name,
- batch->exec_bos[i],
- (flags & EXEC_OBJECT_WRITE) ? "(write)" : "",
batch->validation_list[i].offset,
batch->exec_bos[i]->size,
- batch->exec_bos[i]->refcount);
+ batch->exec_bos[i]->refcount,
+ (flags & EXEC_OBJECT_WRITE) ? " (write)" : "");
}
}
+/**
+ * Return BO information to the batch decoder (for debugging).
+ */
static struct gen_batch_decode_bo
-decode_get_bo(void *v_batch, uint64_t address)
+decode_get_bo(void *v_batch, bool ppgtt, uint64_t address)
{
struct iris_batch *batch = v_batch;
+ assert(ppgtt);
+
for (int i = 0; i < batch->exec_count; i++) {
struct iris_bo *bo = batch->exec_bos[i];
/* The decoder zeroes out the top 16 bits, so we need to as well */
return (struct gen_batch_decode_bo) { };
}
-static bool
-uint_key_compare(const void *a, const void *b)
+static unsigned
+decode_get_state_size(void *v_batch,
+ uint64_t address,
+ UNUSED uint64_t base_address)
{
- return a == b;
+ struct iris_batch *batch = v_batch;
+ unsigned size = (uintptr_t)
+ _mesa_hash_table_u64_search(batch->state_sizes, address);
+
+ return size;
}
-static uint32_t
-uint_key_hash(const void *key)
+/**
+ * Decode the current batch.
+ */
+static void
+decode_batch(struct iris_batch *batch)
{
- return (uintptr_t) key;
+ void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
+ gen_print_batch(&batch->decoder, map, batch->primary_batch_size,
+ batch->exec_bos[0]->gtt_offset, false);
}
void
struct iris_screen *screen,
struct iris_vtable *vtbl,
struct pipe_debug_callback *dbg,
- uint8_t ring)
+ struct pipe_device_reset_callback *reset,
+ struct hash_table_u64 *state_sizes,
+ struct iris_batch *all_batches,
+ enum iris_batch_name name,
+ int priority)
{
batch->screen = screen;
batch->vtbl = vtbl;
batch->dbg = dbg;
+ batch->reset = reset;
+ batch->state_sizes = state_sizes;
+ batch->name = name;
+
+ batch->hw_ctx_id = iris_create_hw_context(screen->bufmgr);
+ assert(batch->hw_ctx_id);
+
+ iris_hw_context_set_priority(screen->bufmgr, batch->hw_ctx_id, priority);
- /* ring should be one of I915_EXEC_RENDER, I915_EXEC_BLT, etc. */
- assert((ring & ~I915_EXEC_RING_MASK) == 0);
- assert(util_bitcount(ring) == 1);
- batch->ring = ring;
+ util_dynarray_init(&batch->exec_fences, ralloc_context(NULL));
+ util_dynarray_init(&batch->syncpts, ralloc_context(NULL));
batch->exec_count = 0;
batch->exec_array_size = 100;
batch->validation_list =
malloc(batch->exec_array_size * sizeof(batch->validation_list[0]));
- batch->binder.bo = NULL;
-
batch->cache.render = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
batch->cache.depth = _mesa_set_create(NULL, _mesa_hash_pointer,
_mesa_key_pointer_equal);
- if (unlikely(INTEL_DEBUG)) {
- batch->state_sizes =
- _mesa_hash_table_create(NULL, uint_key_hash, uint_key_compare);
+ memset(batch->other_batches, 0, sizeof(batch->other_batches));
+
+ for (int i = 0, j = 0; i < IRIS_BATCH_COUNT; i++) {
+ if (&all_batches[i] != batch)
+ batch->other_batches[j++] = &all_batches[i];
+ }
+
+ if (unlikely(INTEL_DEBUG)) {
const unsigned decode_flags =
GEN_BATCH_DECODE_FULL |
((INTEL_DEBUG & DEBUG_COLOR) ? GEN_BATCH_DECODE_IN_COLOR : 0) |
gen_batch_decode_ctx_init(&batch->decoder, &screen->devinfo,
stderr, decode_flags, NULL,
- decode_get_bo, NULL, batch);
+ decode_get_bo, decode_get_state_size, batch);
+ batch->decoder.dynamic_base = IRIS_MEMZONE_DYNAMIC_START;
+ batch->decoder.instruction_base = IRIS_MEMZONE_SHADER_START;
batch->decoder.max_vbo_decoded_lines = 32;
}
iris_batch_reset(batch);
}
-#define READ_ONCE(x) (*(volatile __typeof__(x) *)&(x))
-
-static unsigned
-add_exec_bo(struct iris_batch *batch, struct iris_bo *bo)
+static struct drm_i915_gem_exec_object2 *
+find_validation_entry(struct iris_batch *batch, struct iris_bo *bo)
{
unsigned index = READ_ONCE(bo->index);
if (index < batch->exec_count && batch->exec_bos[index] == bo)
- return index;
+ return &batch->validation_list[index];
/* May have been shared between multiple active batches */
for (index = 0; index < batch->exec_count; index++) {
if (batch->exec_bos[index] == bo)
- return index;
+ return &batch->validation_list[index];
}
- iris_bo_reference(bo);
+ return NULL;
+}
- if (batch->exec_count == batch->exec_array_size) {
+static void
+ensure_exec_obj_space(struct iris_batch *batch, uint32_t count)
+{
+ while (batch->exec_count + count > batch->exec_array_size) {
batch->exec_array_size *= 2;
batch->exec_bos =
realloc(batch->exec_bos,
realloc(batch->validation_list,
batch->exec_array_size * sizeof(batch->validation_list[0]));
}
+}
+
+/**
+ * Add a buffer to the current batch's validation list.
+ *
+ * You must call this on any BO you wish to use in this batch, to ensure
+ * that it's resident when the GPU commands execute.
+ */
+void
+iris_use_pinned_bo(struct iris_batch *batch,
+ struct iris_bo *bo,
+ bool writable)
+{
+ assert(bo->kflags & EXEC_OBJECT_PINNED);
+
+ /* Never mark the workaround BO with EXEC_OBJECT_WRITE. We don't care
+ * about the order of any writes to that buffer, and marking it writable
+ * would introduce data dependencies between multiple batches which share
+ * the buffer.
+ */
+ if (bo == batch->screen->workaround_bo)
+ writable = false;
+
+ struct drm_i915_gem_exec_object2 *existing_entry =
+ find_validation_entry(batch, bo);
+
+ if (existing_entry) {
+ /* The BO is already in the validation list; mark it writable */
+ if (writable)
+ existing_entry->flags |= EXEC_OBJECT_WRITE;
+
+ return;
+ }
+
+ if (bo != batch->bo) {
+ /* This is the first time our batch has seen this BO. Before we use it,
+ * we may need to flush and synchronize with other batches.
+ */
+ for (int b = 0; b < ARRAY_SIZE(batch->other_batches); b++) {
+ struct drm_i915_gem_exec_object2 *other_entry =
+ find_validation_entry(batch->other_batches[b], bo);
+
+ /* If the buffer is referenced by another batch, and either batch
+ * intends to write it, then flush the other batch and synchronize.
+ *
+ * Consider these cases:
+ *
+ * 1. They read, we read => No synchronization required.
+ * 2. They read, we write => Synchronize (they need the old value)
+ * 3. They write, we read => Synchronize (we need their new value)
+ * 4. They write, we write => Synchronize (order writes)
+ *
+ * The read/read case is very common, as multiple batches usually
+ * share a streaming state buffer or shader assembly buffer, and
+ * we want to avoid synchronizing in this case.
+ */
+ if (other_entry &&
+ ((other_entry->flags & EXEC_OBJECT_WRITE) || writable)) {
+ iris_batch_flush(batch->other_batches[b]);
+ iris_batch_add_syncpt(batch, batch->other_batches[b]->last_syncpt,
+ I915_EXEC_FENCE_WAIT);
+ }
+ }
+ }
+
+ /* Now, take a reference and add it to the validation list. */
+ iris_bo_reference(bo);
+
+ ensure_exec_obj_space(batch, 1);
batch->validation_list[batch->exec_count] =
(struct drm_i915_gem_exec_object2) {
.handle = bo->gem_handle,
.offset = bo->gtt_offset,
- .flags = bo->kflags,
+ .flags = bo->kflags | (writable ? EXEC_OBJECT_WRITE : 0),
};
bo->index = batch->exec_count;
batch->exec_bos[batch->exec_count] = bo;
batch->aperture_space += bo->size;
- return batch->exec_count++;
+ batch->exec_count++;
}
static void
batch->bo->kflags |= EXEC_OBJECT_CAPTURE;
batch->map = iris_bo_map(NULL, batch->bo, MAP_READ | MAP_WRITE);
batch->map_next = batch->map;
- batch->contains_draw = false;
- add_exec_bo(batch, batch->bo);
+ iris_use_pinned_bo(batch, batch->bo, false);
}
static void
-iris_batch_reset(struct iris_batch *batch)
+iris_batch_maybe_noop(struct iris_batch *batch)
{
- if (batch->last_bo != NULL) {
- iris_bo_unreference(batch->last_bo);
- batch->last_bo = NULL;
+ /* We only insert the NOOP at the beginning of the batch. */
+ assert(iris_batch_bytes_used(batch) == 0);
+
+ if (batch->noop_enabled) {
+ /* Emit MI_BATCH_BUFFER_END to prevent any further command to be
+ * executed.
+ */
+ uint32_t *map = batch->map_next;
+
+ map[0] = (0xA << 23);
+
+ batch->map_next += 4;
}
- batch->last_bo = batch->bo;
+}
+
+static void
+iris_batch_reset(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+
+ iris_bo_unreference(batch->bo);
batch->primary_batch_size = 0;
+ batch->total_chained_batch_size = 0;
+ batch->contains_draw = false;
+ batch->decoder.surface_base = batch->last_surface_base_address;
create_batch(batch);
assert(batch->bo->index == 0);
- iris_destroy_binder(&batch->binder);
- iris_init_binder(&batch->binder, batch->bo->bufmgr);
-
- if (batch->state_sizes)
- _mesa_hash_table_clear(batch->state_sizes, NULL);
+ struct iris_syncpt *syncpt = iris_create_syncpt(screen);
+ iris_batch_add_syncpt(batch, syncpt, I915_EXEC_FENCE_SIGNAL);
+ iris_syncpt_reference(screen, &syncpt, NULL);
iris_cache_sets_clear(batch);
+
+ iris_batch_maybe_noop(batch);
}
void
iris_batch_free(struct iris_batch *batch)
{
+ struct iris_screen *screen = batch->screen;
+ struct iris_bufmgr *bufmgr = screen->bufmgr;
+
for (int i = 0; i < batch->exec_count; i++) {
iris_bo_unreference(batch->exec_bos[i]);
}
free(batch->exec_bos);
free(batch->validation_list);
+
+ ralloc_free(batch->exec_fences.mem_ctx);
+
+ util_dynarray_foreach(&batch->syncpts, struct iris_syncpt *, s)
+ iris_syncpt_reference(screen, s, NULL);
+ ralloc_free(batch->syncpts.mem_ctx);
+
+ iris_syncpt_reference(screen, &batch->last_syncpt, NULL);
+
iris_bo_unreference(batch->bo);
batch->bo = NULL;
batch->map = NULL;
batch->map_next = NULL;
- iris_bo_unreference(batch->last_bo);
+ iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
_mesa_hash_table_destroy(batch->cache.render, NULL);
_mesa_set_destroy(batch->cache.depth, NULL);
- iris_destroy_binder(&batch->binder);
-
- if (batch->state_sizes) {
- _mesa_hash_table_destroy(batch->state_sizes, NULL);
+ if (unlikely(INTEL_DEBUG))
gen_batch_decode_ctx_finish(&batch->decoder);
- }
-}
-
-static unsigned
-batch_bytes_used(struct iris_batch *batch)
-{
- return batch->map_next - batch->map;
}
/**
iris_batch_maybe_flush(struct iris_batch *batch, unsigned estimate)
{
if (batch->bo != batch->exec_bos[0] ||
- batch_bytes_used(batch) + estimate >= BATCH_SZ) {
+ iris_batch_bytes_used(batch) + estimate >= BATCH_SZ) {
iris_batch_flush(batch);
}
}
-void
-iris_require_command_space(struct iris_batch *batch, unsigned size)
+static void
+record_batch_sizes(struct iris_batch *batch)
{
- const unsigned required_bytes = batch_bytes_used(batch) + size;
-
- if (required_bytes >= BATCH_SZ) {
- /* We only support chaining a single time. */
- assert(batch->bo == batch->exec_bos[0]);
-
- uint32_t *cmd = batch->map_next;
- uint64_t *addr = batch->map_next + 4;
- uint32_t *noop = batch->map_next + 12;
- batch->map_next += 12;
-
- /* No longer held by batch->bo, still held by validation list */
- iris_bo_unreference(batch->bo);
- batch->primary_batch_size = ALIGN(batch_bytes_used(batch), 8);
- create_batch(batch);
-
- /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
- *cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
- *addr = batch->bo->gtt_offset;
- *noop = 0;
- }
+ unsigned batch_size = iris_batch_bytes_used(batch);
+
+ VG(VALGRIND_CHECK_MEM_IS_DEFINED(batch->map, batch_size));
+
+ if (batch->bo == batch->exec_bos[0])
+ batch->primary_batch_size = batch_size;
+
+ batch->total_chained_batch_size += batch_size;
}
-void *
-iris_get_command_space(struct iris_batch *batch, unsigned bytes)
+void
+iris_chain_to_new_batch(struct iris_batch *batch)
{
- iris_require_command_space(batch, bytes);
- void *map = batch->map_next;
- batch->map_next += bytes;
- return map;
+ uint32_t *cmd = batch->map_next;
+ uint64_t *addr = batch->map_next + 4;
+ batch->map_next += 12;
+
+ record_batch_sizes(batch);
+
+ /* No longer held by batch->bo, still held by validation list */
+ iris_bo_unreference(batch->bo);
+ create_batch(batch);
+
+ /* Emit MI_BATCH_BUFFER_START to chain to another batch. */
+ *cmd = (0x31 << 23) | (1 << 8) | (3 - 2);
+ *addr = batch->bo->gtt_offset;
}
-void
-iris_batch_emit(struct iris_batch *batch, const void *data, unsigned size)
+static void
+add_aux_map_bos_to_batch(struct iris_batch *batch)
{
- void *map = iris_get_command_space(batch, size);
- memcpy(map, data, size);
+ void *aux_map_ctx = iris_bufmgr_get_aux_map_context(batch->screen->bufmgr);
+ if (!aux_map_ctx)
+ return;
+
+ uint32_t count = gen_aux_map_get_num_buffers(aux_map_ctx);
+ ensure_exec_obj_space(batch, count);
+ gen_aux_map_fill_bos(aux_map_ctx,
+ (void**)&batch->exec_bos[batch->exec_count], count);
+ for (uint32_t i = 0; i < count; i++) {
+ struct iris_bo *bo = batch->exec_bos[batch->exec_count];
+ iris_bo_reference(bo);
+ batch->validation_list[batch->exec_count] =
+ (struct drm_i915_gem_exec_object2) {
+ .handle = bo->gem_handle,
+ .offset = bo->gtt_offset,
+ .flags = bo->kflags,
+ };
+ batch->aperture_space += bo->size;
+ batch->exec_count++;
+ }
}
/**
- * Called from iris_batch_flush before emitting MI_BATCHBUFFER_END and
- * sending it off.
- *
- * This function can emit state (say, to preserve registers that aren't saved
- * between batches).
+ * Terminate a batch with MI_BATCH_BUFFER_END.
*/
static void
iris_finish_batch(struct iris_batch *batch)
{
- if (batch->bo == batch->exec_bos[0])
- batch->primary_batch_size = batch_bytes_used(batch);
-
- // XXX: ISP DIS
+ add_aux_map_bos_to_batch(batch);
- /* Emit MI_BATCH_BUFFER_END to finish our batch. Note that execbuf2
- * requires our batch size to be QWord aligned, so we pad it out if
- * necessary by emitting an extra MI_NOOP after the end.
- */
- const bool qword_aligned = (batch_bytes_used(batch) % 8) == 0;
+ /* Emit MI_BATCH_BUFFER_END to finish our batch. */
uint32_t *map = batch->map_next;
map[0] = (0xA << 23);
- map[1] = 0;
- batch->map_next += qword_aligned ? 8 : 4;
+ batch->map_next += 4;
+
+ record_batch_sizes(batch);
}
+/**
+ * Replace our current GEM context with a new one (in case it got banned).
+ */
+static bool
+replace_hw_ctx(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ struct iris_bufmgr *bufmgr = screen->bufmgr;
+
+ uint32_t new_ctx = iris_clone_hw_context(bufmgr, batch->hw_ctx_id);
+ if (!new_ctx)
+ return false;
+
+ iris_destroy_hw_context(bufmgr, batch->hw_ctx_id);
+ batch->hw_ctx_id = new_ctx;
+
+ /* Notify the context that state must be re-initialized. */
+ iris_lost_context_state(batch);
+
+ return true;
+}
+
+enum pipe_reset_status
+iris_batch_check_for_reset(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ enum pipe_reset_status status = PIPE_NO_RESET;
+ struct drm_i915_reset_stats stats = { .ctx_id = batch->hw_ctx_id };
+
+ if (drmIoctl(screen->fd, DRM_IOCTL_I915_GET_RESET_STATS, &stats))
+ DBG("DRM_IOCTL_I915_GET_RESET_STATS failed: %s\n", strerror(errno));
+
+ if (stats.batch_active != 0) {
+ /* A reset was observed while a batch from this hardware context was
+ * executing. Assume that this context was at fault.
+ */
+ status = PIPE_GUILTY_CONTEXT_RESET;
+ } else if (stats.batch_pending != 0) {
+ /* A reset was observed while a batch from this context was in progress,
+ * but the batch was not executing. In this case, assume that the
+ * context was not at fault.
+ */
+ status = PIPE_INNOCENT_CONTEXT_RESET;
+ }
+
+ if (status != PIPE_NO_RESET) {
+ /* Our context is likely banned, or at least in an unknown state.
+ * Throw it away and start with a fresh context. Ideally this may
+ * catch the problem before our next execbuf fails with -EIO.
+ */
+ replace_hw_ctx(batch);
+ }
+
+ return status;
+}
+
+/**
+ * Submit the batch to the GPU via execbuffer2.
+ */
static int
-submit_batch(struct iris_batch *batch, int in_fence_fd, int *out_fence_fd)
+submit_batch(struct iris_batch *batch)
{
iris_bo_unmap(batch->bo);
.buffers_ptr = (uintptr_t) batch->validation_list,
.buffer_count = batch->exec_count,
.batch_start_offset = 0,
- .batch_len = batch->primary_batch_size,
- .flags = batch->ring |
+ /* This must be QWord aligned. */
+ .batch_len = ALIGN(batch->primary_batch_size, 8),
+ .flags = I915_EXEC_RENDER |
I915_EXEC_NO_RELOC |
I915_EXEC_BATCH_FIRST |
I915_EXEC_HANDLE_LUT,
.rsvd1 = batch->hw_ctx_id, /* rsvd1 is actually the context ID */
};
- unsigned long cmd = DRM_IOCTL_I915_GEM_EXECBUFFER2;
-
- if (in_fence_fd != -1) {
- execbuf.rsvd2 = in_fence_fd;
- execbuf.flags |= I915_EXEC_FENCE_IN;
+ if (num_fences(batch)) {
+ execbuf.flags |= I915_EXEC_FENCE_ARRAY;
+ execbuf.num_cliprects = num_fences(batch);
+ execbuf.cliprects_ptr =
+ (uintptr_t)util_dynarray_begin(&batch->exec_fences);
}
- if (out_fence_fd != NULL) {
- cmd = DRM_IOCTL_I915_GEM_EXECBUFFER2_WR;
- *out_fence_fd = -1;
- execbuf.flags |= I915_EXEC_FENCE_OUT;
- }
-
- int ret = drm_ioctl(batch->screen->fd, cmd, &execbuf);
- if (ret != 0) {
+ int ret = 0;
+ if (!batch->screen->no_hw &&
+ gen_ioctl(batch->screen->fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf))
ret = -errno;
- DBG("execbuf FAILED: errno = %d\n", -ret);
- } else {
- DBG("execbuf succeeded\n");
- }
for (int i = 0; i < batch->exec_count; i++) {
struct iris_bo *bo = batch->exec_bos[i];
bo->idle = false;
bo->index = -1;
- }
- if (ret == 0 && out_fence_fd != NULL)
- *out_fence_fd = execbuf.rsvd2 >> 32;
+ iris_bo_unreference(bo);
+ }
return ret;
}
+static const char *
+batch_name_to_string(enum iris_batch_name name)
+{
+ const char *names[IRIS_BATCH_COUNT] = {
+ [IRIS_BATCH_RENDER] = "render",
+ [IRIS_BATCH_COMPUTE] = "compute",
+ };
+ return names[name];
+}
+
/**
- * The in_fence_fd is ignored if -1. Otherwise this function takes ownership
- * of the fd.
+ * Flush the batch buffer, submitting it to the GPU and resetting it so
+ * we're ready to emit the next batch.
+ *
+ * \param in_fence_fd is ignored if -1. Otherwise, this function takes
+ * ownership of the fd.
*
- * The out_fence_fd is ignored if NULL. Otherwise, the caller takes ownership
- * of the returned fd.
+ * \param out_fence_fd is ignored if NULL. Otherwise, the caller must
+ * take ownership of the returned fd.
*/
-int
-_iris_batch_flush_fence(struct iris_batch *batch,
- int in_fence_fd, int *out_fence_fd,
- const char *file, int line)
+void
+_iris_batch_flush(struct iris_batch *batch, const char *file, int line)
{
- if (batch_bytes_used(batch) == 0)
- return 0;
+ struct iris_screen *screen = batch->screen;
+
+ if (iris_batch_bytes_used(batch) == 0)
+ return;
iris_finish_batch(batch);
- if (unlikely(INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT))) {
- int bytes_for_commands = batch_bytes_used(batch);
- int bytes_for_binder = batch->binder.insert_point;
- int second_bytes = 0;
- if (batch->bo != batch->exec_bos[0]) {
- second_bytes = bytes_for_commands;
- bytes_for_commands += batch->primary_batch_size;
- }
- fprintf(stderr, "%19s:%-3d: Batchbuffer flush with %5d+%5db (%0.1f%%) "
- "(cmds), %5db (%0.1f%%) (binder), %4d BOs (%0.1fMb aperture)\n",
- file, line,
- batch->primary_batch_size, second_bytes,
- 100.0f * bytes_for_commands / BATCH_SZ,
- bytes_for_binder, 100.0f * bytes_for_binder / IRIS_BINDER_SIZE,
+ if (unlikely(INTEL_DEBUG &
+ (DEBUG_BATCH | DEBUG_SUBMIT | DEBUG_PIPE_CONTROL))) {
+ const char *basefile = strstr(file, "iris/");
+ if (basefile)
+ file = basefile + 5;
+
+ fprintf(stderr, "%19s:%-3d: %s batch [%u] flush with %5db (%0.1f%%) "
+ "(cmds), %4d BOs (%0.1fMb aperture)\n",
+ file, line, batch_name_to_string(batch->name), batch->hw_ctx_id,
+ batch->total_chained_batch_size,
+ 100.0f * batch->total_chained_batch_size / BATCH_SZ,
batch->exec_count,
(float) batch->aperture_space / (1024 * 1024));
- dump_validation_list(batch);
- }
- if (unlikely(INTEL_DEBUG & DEBUG_BATCH)) {
- decode_batch(batch);
+ if (INTEL_DEBUG & (DEBUG_BATCH | DEBUG_SUBMIT)) {
+ dump_fence_list(batch);
+ dump_validation_list(batch);
+ }
+
+ if (INTEL_DEBUG & DEBUG_BATCH) {
+ decode_batch(batch);
+ }
}
- int ret = submit_batch(batch, in_fence_fd, out_fence_fd);
+ int ret = submit_batch(batch);
- //throttle(iris);
+ batch->exec_count = 0;
+ batch->aperture_space = 0;
- if (ret >= 0) {
- //if (iris->ctx.Const.ResetStrategy == GL_LOSE_CONTEXT_ON_RESET_ARB)
- //iris_check_for_reset(ice);
+ struct iris_syncpt *syncpt =
+ ((struct iris_syncpt **) util_dynarray_begin(&batch->syncpts))[0];
+ iris_syncpt_reference(screen, &batch->last_syncpt, syncpt);
- if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
- dbg_printf("waiting for idle\n");
- iris_bo_wait_rendering(batch->bo);
- }
- } else {
-#ifdef DEBUG
- fprintf(stderr, "iris: Failed to submit batchbuffer: %s\n",
- strerror(-ret));
- abort();
-#endif
- }
+ util_dynarray_foreach(&batch->syncpts, struct iris_syncpt *, s)
+ iris_syncpt_reference(screen, s, NULL);
+ util_dynarray_clear(&batch->syncpts);
- /* Clean up after the batch we submitted and prepare for a new one. */
- for (int i = 0; i < batch->exec_count; i++) {
- iris_bo_unreference(batch->exec_bos[i]);
- batch->exec_bos[i] = NULL;
+ util_dynarray_clear(&batch->exec_fences);
+
+ if (unlikely(INTEL_DEBUG & DEBUG_SYNC)) {
+ dbg_printf("waiting for idle\n");
+ iris_bo_wait_rendering(batch->bo); /* if execbuf failed; this is a nop */
}
- batch->exec_count = 0;
- batch->aperture_space = 0;
/* Start a new batch buffer. */
iris_batch_reset(batch);
- return 0;
-}
+ /* EIO means our context is banned. In this case, try and replace it
+ * with a new logical context, and inform iris_context that all state
+ * has been lost and needs to be re-initialized. If this succeeds,
+ * dubiously claim success...
+ */
+ if (ret == -EIO && replace_hw_ctx(batch)) {
+ if (batch->reset->reset) {
+ /* Tell the state tracker the device is lost and it was our fault. */
+ batch->reset->reset(batch->reset->data, PIPE_GUILTY_CONTEXT_RESET);
+ }
-bool
-iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
-{
- unsigned index = READ_ONCE(bo->index);
- if (index < batch->exec_count && batch->exec_bos[index] == bo)
- return true;
+ ret = 0;
+ }
- for (int i = 0; i < batch->exec_count; i++) {
- if (batch->exec_bos[i] == bo)
- return true;
+ if (ret < 0) {
+#ifdef DEBUG
+ const bool color = INTEL_DEBUG & DEBUG_COLOR;
+ fprintf(stderr, "%siris: Failed to submit batchbuffer: %-80s%s\n",
+ color ? "\e[1;41m" : "", strerror(-ret), color ? "\e[0m" : "");
+#endif
+ abort();
}
- return false;
}
-/* This is the only way buffers get added to the validate list.
+/**
+ * Does the current batch refer to the given BO?
+ *
+ * (In other words, is the BO in the current batch's validation list?)
*/
-void
-iris_use_pinned_bo(struct iris_batch *batch,
- struct iris_bo *bo,
- bool writable)
+bool
+iris_batch_references(struct iris_batch *batch, struct iris_bo *bo)
{
- assert(bo->kflags & EXEC_OBJECT_PINNED);
- unsigned index = add_exec_bo(batch, bo);
- if (writable)
- batch->validation_list[index].flags |= EXEC_OBJECT_WRITE;
+ return find_validation_entry(batch, bo) != NULL;
}
-static void
-decode_batch(struct iris_batch *batch)
+/**
+ * Updates the state of the noop feature.
+ */
+uint64_t
+iris_batch_prepare_noop(struct iris_batch *batch, bool noop_enable, uint64_t dirty_flags)
{
- //if (batch->bo != batch->exec_bos[0]) {
- void *map = iris_bo_map(batch->dbg, batch->exec_bos[0], MAP_READ);
- gen_print_batch(&batch->decoder, map, batch->primary_batch_size,
- batch->exec_bos[0]->gtt_offset);
+ if (batch->noop_enabled == noop_enable)
+ return 0;
- //fprintf(stderr, "Secondary batch...\n");
- //}
+ batch->noop_enabled = noop_enable;
- //gen_print_batch(&batch->decoder, batch->map, batch_bytes_used(batch),
- //batch->bo->gtt_offset);
+ iris_batch_flush(batch);
+
+ /* If the batch was empty, flush had no effect, so insert our noop. */
+ if (iris_batch_bytes_used(batch) == 0)
+ iris_batch_maybe_noop(batch);
+
+ /* We only need to update the entire state if we transition from noop ->
+ * not-noop.
+ */
+ return !batch->noop_enabled ? dirty_flags : 0;
}
projects / mesa.git / blobdiff