iris: Remove the CCS_D fallback

[mesa.git] / src / gallium / drivers / iris / iris_blorp.c

diff --git a/src/gallium/drivers/iris/iris_blorp.c b/src/gallium/drivers/iris/iris_blorp.c
index 1da234d9467fea63f7c0059cf1388e28bd2e35f5..34f40f7fa614162bfdb4665d0336d5787757e54d 100644 (file)
--- a/src/gallium/drivers/iris/iris_blorp.c
+++ b/src/gallium/drivers/iris/iris_blorp.c
@@ -60,7 +60,7 @@ stream_state(struct iris_batch *batch,
    u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
 
    struct iris_bo *bo = iris_resource_bo(res);
-   iris_use_pinned_bo(batch, bo, false);
+   iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
 
    iris_record_state_size(batch->state_sizes,
                           bo->gtt_offset + *out_offset, size);
@@ -93,7 +93,8 @@ combine_and_pin_address(struct blorp_batch *blorp_batch,
    struct iris_batch *batch = blorp_batch->driver_batch;
    struct iris_bo *bo = addr.buffer;
 
-   iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
+   iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE,
+                      IRIS_DOMAIN_NONE);
 
    /* Assume this is a general address, not relative to a base. */
    return bo->gtt_offset + addr.offset;
@@ -162,7 +163,7 @@ blorp_alloc_binding_table(struct blorp_batch *blorp_batch,
       bt_map[i] = surface_offsets[i] - (uint32_t) binder->bo->gtt_offset;
    }
 
-   iris_use_pinned_bo(batch, binder->bo, false);
+   iris_use_pinned_bo(batch, binder->bo, false, IRIS_DOMAIN_NONE);
 
    batch->screen->vtbl.update_surface_base_address(batch, binder);
 }
@@ -273,24 +274,17 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
                                 PIPE_CONTROL_STALL_AT_SCOREBOARD);
 #endif
 
-   /* Flush the sampler and render caches.  We definitely need to flush the
-    * sampler cache so that we get updated contents from the render cache for
-    * the glBlitFramebuffer() source.  Also, we are sometimes warned in the
-    * docs to flush the cache between reinterpretations of the same surface
-    * data with different formats, which blorp does for stencil and depth
-    * data.
+   /* Flush the render cache in cases where the same surface is reinterpreted
+    * with a differernt format, which blorp does for stencil and depth data
+    * among other things.  Invalidation of sampler caches and flushing of any
+    * caches which had previously written the source surfaces should already
+    * have been handled by the caller.
     */
-   if (params->src.enabled)
-      iris_cache_flush_for_read(batch, params->src.addr.buffer);
    if (params->dst.enabled) {
       iris_cache_flush_for_render(batch, params->dst.addr.buffer,
                                   params->dst.view.format,
                                   params->dst.aux_usage);
    }
-   if (params->depth.enabled)
-      iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
-   if (params->stencil.enabled)
-      iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
 
    iris_require_command_space(batch, 1400);
 
@@ -366,15 +360,18 @@ iris_blorp_exec(struct blorp_batch *blorp_batch,
    ice->state.dirty |= ~skip_bits;
    ice->state.stage_dirty |= ~skip_stage_bits;
 
-   if (params->dst.enabled) {
-      iris_render_cache_add_bo(batch, params->dst.addr.buffer,
-                               params->dst.view.format,
-                               params->dst.aux_usage);
-   }
+   if (params->src.enabled)
+      iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno,
+                         IRIS_DOMAIN_OTHER_READ);
+   if (params->dst.enabled)
+      iris_bo_bump_seqno(params->dst.addr.buffer, batch->next_seqno,
+                         IRIS_DOMAIN_RENDER_WRITE);
    if (params->depth.enabled)
-      iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
+      iris_bo_bump_seqno(params->depth.addr.buffer, batch->next_seqno,
+                         IRIS_DOMAIN_DEPTH_WRITE);
    if (params->stencil.enabled)
-      iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
+      iris_bo_bump_seqno(params->stencil.addr.buffer, batch->next_seqno,
+                         IRIS_DOMAIN_DEPTH_WRITE);
 }
 
 void