* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
*
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
*
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
*/
+
+/**
+ * @file iris_blorp.c
+ *
+ * ============================= GENXML CODE =============================
+ * [This file is compiled once per generation.]
+ * =======================================================================
+ *
+ * GenX specific code for working with BLORP (blitting, resolves, clears
+ * on the 3D engine). This provides the driver-specific hooks needed to
+ * implement the BLORP API.
+ *
+ * See iris_blit.c, iris_clear.c, and so on.
+ */
+
#include <assert.h>
#include "iris_batch.h"
#include "iris_resource.h"
#include "iris_context.h"
-#include "blorp/blorp_genX_exec.h"
#include "util/u_upload_mgr.h"
+#include "intel/common/gen_l3_config.h"
+
+#define BLORP_USE_SOFTPIN
+#include "blorp/blorp_genX_exec.h"
static uint32_t *
stream_state(struct iris_batch *batch,
u_upload_alloc(uploader, 0, size, alignment, out_offset, &res, &ptr);
- *out_bo = iris_resource_bo(res);
- iris_use_pinned_bo(batch, *out_bo, false);
+ struct iris_bo *bo = iris_resource_bo(res);
+ iris_use_pinned_bo(batch, bo, false, IRIS_DOMAIN_NONE);
+
+ iris_record_state_size(batch->state_sizes,
+ bo->gtt_offset + *out_offset, size);
- *out_offset += iris_bo_offset_from_base_address(*out_bo);
+ /* If the caller has asked for a BO, we leave them the responsibility of
+ * adding bo->gtt_offset (say, by handing an address to genxml). If not,
+ * we assume they want the offset from a base address.
+ */
+ if (out_bo)
+ *out_bo = bo;
+ else
+ *out_offset += iris_bo_offset_from_base_address(bo);
pipe_resource_reference(&res, NULL);
struct iris_batch *batch = blorp_batch->driver_batch;
struct iris_bo *bo = addr.buffer;
- iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE);
+ iris_use_pinned_bo(batch, bo, addr.reloc_flags & RELOC_WRITE,
+ IRIS_DOMAIN_NONE);
/* Assume this is a general address, not relative to a base. */
return bo->gtt_offset + addr.offset;
UNUSED static struct blorp_address
blorp_get_surface_base_address(UNUSED struct blorp_batch *blorp_batch)
{
- return (struct blorp_address) { .offset = IRIS_MEMZONE_SURFACE_START };
+ return (struct blorp_address) { .offset = IRIS_MEMZONE_BINDER_START };
}
static void *
{
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
- struct iris_bo *bo;
return stream_state(batch, ice->state.dynamic_uploader,
- size, alignment, offset, &bo);
+ size, alignment, offset, NULL);
}
static void
void **surface_maps)
{
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
+ struct iris_binder *binder = &ice->state.binder;
struct iris_batch *batch = blorp_batch->driver_batch;
- struct iris_bo *bo;
- uint32_t *bt_map = iris_binder_reserve(&ice->state.binder,
- num_entries * sizeof(uint32_t),
- bt_offset);
+ *bt_offset = iris_binder_reserve(ice, num_entries * sizeof(uint32_t));
+ uint32_t *bt_map = binder->map + *bt_offset;
for (unsigned i = 0; i < num_entries; i++) {
surface_maps[i] = stream_state(batch, ice->state.surface_uploader,
state_size, state_alignment,
- &surface_offsets[i], &bo);
- bt_map[i] = surface_offsets[i];
+ &surface_offsets[i], NULL);
+ bt_map[i] = surface_offsets[i] - (uint32_t) binder->bo->gtt_offset;
}
+
+ iris_use_pinned_bo(batch, binder->bo, false, IRIS_DOMAIN_NONE);
+
+ batch->screen->vtbl.update_surface_base_address(batch, binder);
}
static void *
*addr = (struct blorp_address) {
.buffer = bo,
.offset = offset,
- // XXX: Broadwell MOCS
- .mocs = I915_MOCS_CACHED,
+ .mocs = iris_mocs(bo, &batch->screen->isl_dev),
};
return map;
}
/**
- * See vf_invalidate_for_vb_48b_transitions in iris_state.c.
- * XXX: actually add this
+ * See iris_upload_render_state's IRIS_DIRTY_VERTEX_BUFFERS handling for
+ * a comment about why these VF invalidations are needed.
*/
static void
-blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch,
+blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *blorp_batch,
const struct blorp_address *addrs,
+ UNUSED uint32_t *sizes,
unsigned num_vbs)
{
-#if 0
+#if GEN_GEN < 11
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
bool need_invalidate = false;
for (unsigned i = 0; i < num_vbs; i++) {
struct iris_bo *bo = addrs[i].buffer;
- uint16_t high_bits = bo ? bo->gtt_offset >> 32u : 0;
+ uint16_t high_bits = bo->gtt_offset >> 32u;
if (high_bits != ice->state.last_vbo_high_bits[i]) {
need_invalidate = true;
}
if (need_invalidate) {
- iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
+ iris_emit_pipe_control_flush(batch,
+ "workaround: VF cache 32-bit key [blorp]",
+ PIPE_CONTROL_VF_CACHE_INVALIDATE |
+ PIPE_CONTROL_CS_STALL);
}
#endif
}
static struct blorp_address
-blorp_get_workaround_page(struct blorp_batch *blorp_batch)
+blorp_get_workaround_address(struct blorp_batch *blorp_batch)
{
struct iris_batch *batch = blorp_batch->driver_batch;
- return (struct blorp_address) { .buffer = batch->screen->workaround_bo };
+ return (struct blorp_address) {
+ .buffer = batch->screen->workaround_address.bo,
+ .offset = batch->screen->workaround_address.offset,
+ };
}
static void
*/
}
-static void
-blorp_emit_urb_config(struct blorp_batch *blorp_batch,
- unsigned vs_entry_size,
- UNUSED unsigned sf_entry_size)
+static const struct gen_l3_config *
+blorp_get_l3_config(struct blorp_batch *blorp_batch)
{
- // XXX: URB...
-#if 0
- if (ice->urb.vsize >= vs_entry_size)
- return;
-
- gen7_upload_urb(ice, vs_entry_size, false, false);
-#endif
+ struct iris_batch *batch = blorp_batch->driver_batch;
+ return batch->screen->l3_config_3d;
}
static void
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
- /* Flush the sampler and render caches. We definitely need to flush the
- * sampler cache so that we get updated contents from the render cache for
- * the glBlitFramebuffer() source. Also, we are sometimes warned in the
- * docs to flush the cache between reinterpretations of the same surface
- * data with different formats, which blorp does for stencil and depth
- * data.
+#if GEN_GEN >= 11
+ /* The PIPE_CONTROL command description says:
+ *
+ * "Whenever a Binding Table Index (BTI) used by a Render Target Message
+ * points to a different RENDER_SURFACE_STATE, SW must issue a Render
+ * Target Cache Flush by enabling this bit. When render target flush
+ * is set due to new association of BTI, PS Scoreboard Stall bit must
+ * be set in this packet."
+ */
+ iris_emit_pipe_control_flush(batch,
+ "workaround: RT BTI change [blorp]",
+ PIPE_CONTROL_RENDER_TARGET_FLUSH |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD);
+#endif
+
+ /* Flush the render cache in cases where the same surface is reinterpreted
+ * with a differernt format, which blorp does for stencil and depth data
+ * among other things. Invalidation of sampler caches and flushing of any
+ * caches which had previously written the source surfaces should already
+ * have been handled by the caller.
*/
- if (params->src.enabled)
- iris_cache_flush_for_read(batch, params->src.addr.buffer);
if (params->dst.enabled) {
iris_cache_flush_for_render(batch, params->dst.addr.buffer,
params->dst.view.format,
params->dst.aux_usage);
}
- if (params->depth.enabled)
- iris_cache_flush_for_depth(batch, params->depth.addr.buffer);
- if (params->stencil.enabled)
- iris_cache_flush_for_depth(batch, params->stencil.addr.buffer);
iris_require_command_space(batch, 1400);
- //iris_require_statebuffer_space(ice, 600); // XXX: THIS. Need this.
- batch->no_wrap = true;
-
- // XXX: Emit L3 state
#if GEN_GEN == 8
- // XXX: PMA - gen8_write_pma_stall_bits(ice, 0);
+ genX(update_pma_fix)(ice, batch, false);
#endif
- // XXX: knock this off...land Jason's i965 patches...
- blorp_emit(blorp_batch, GENX(3DSTATE_DRAWING_RECTANGLE), rect) {
- rect.ClippedDrawingRectangleXMax = MAX2(params->x1, params->x0) - 1;
- rect.ClippedDrawingRectangleYMax = MAX2(params->y1, params->y0) - 1;
+ const unsigned scale = params->fast_clear_op ? UINT_MAX : 1;
+ if (ice->state.current_hash_scale != scale) {
+ genX(emit_hashing_mode)(ice, batch, params->x1 - params->x0,
+ params->y1 - params->y0, scale);
}
- blorp_exec(blorp_batch, params);
+#if GEN_GEN >= 12
+ genX(invalidate_aux_map_state)(batch);
+#endif
- batch->no_wrap = false;
+ iris_handle_always_flush_cache(batch);
- // XXX: aperture checks?
+ blorp_exec(blorp_batch, params);
+
+ iris_handle_always_flush_cache(batch);
/* We've smashed all state compared to what the normal 3D pipeline
* rendering tracks for GL.
*/
- // XXX: skip some if (!(batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL))
- ice->state.dirty |= ~(IRIS_DIRTY_POLYGON_STIPPLE |
- IRIS_DIRTY_LINE_STIPPLE);
-
-#if 0
- ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS |
- IRIS_DIRTY_COLOR_CALC_STATE |
- IRIS_DIRTY_CONSTANTS_VS |
- IRIS_DIRTY_CONSTANTS_TCS |
- IRIS_DIRTY_CONSTANTS_TES |
- IRIS_DIRTY_CONSTANTS_GS |
- IRIS_DIRTY_CONSTANTS_PS |
- IRIS_DIRTY_CONSTANTS_PS |
- IRIS_DIRTY_SAMPLER_STATES_VS |
- IRIS_DIRTY_SAMPLER_STATES_TCS |
- IRIS_DIRTY_SAMPLER_STATES_TES |
- IRIS_DIRTY_SAMPLER_STATES_GS |
- IRIS_DIRTY_SAMPLER_STATES_PS |
- IRIS_DIRTY_SAMPLER_STATES_PS |
- IRIS_DIRTY_MULTISAMPLE |
- IRIS_DIRTY_SAMPLE_MASK |
- IRIS_DIRTY_VS |
- IRIS_DIRTY_TCS |
- IRIS_DIRTY_TES |
- // IRIS_DIRTY_STREAMOUT |
- IRIS_DIRTY_GS |
- IRIS_DIRTY_CLIP |
- IRIS_DIRTY_FS |
- IRIS_DIRTY_CC_VIEWPORT |
-#endif
- if (params->dst.enabled) {
- iris_render_cache_add_bo(batch, params->dst.addr.buffer,
- params->dst.view.format,
- params->dst.aux_usage);
+ uint64_t skip_bits = (IRIS_DIRTY_POLYGON_STIPPLE |
+ IRIS_DIRTY_SO_BUFFERS |
+ IRIS_DIRTY_SO_DECL_LIST |
+ IRIS_DIRTY_LINE_STIPPLE |
+ IRIS_ALL_DIRTY_FOR_COMPUTE |
+ IRIS_DIRTY_SCISSOR_RECT |
+ IRIS_DIRTY_VF |
+ IRIS_DIRTY_SF_CL_VIEWPORT);
+ uint64_t skip_stage_bits = (IRIS_ALL_STAGE_DIRTY_FOR_COMPUTE |
+ IRIS_STAGE_DIRTY_UNCOMPILED_VS |
+ IRIS_STAGE_DIRTY_UNCOMPILED_TCS |
+ IRIS_STAGE_DIRTY_UNCOMPILED_TES |
+ IRIS_STAGE_DIRTY_UNCOMPILED_GS |
+ IRIS_STAGE_DIRTY_UNCOMPILED_FS |
+ IRIS_STAGE_DIRTY_SAMPLER_STATES_VS |
+ IRIS_STAGE_DIRTY_SAMPLER_STATES_TCS |
+ IRIS_STAGE_DIRTY_SAMPLER_STATES_TES |
+ IRIS_STAGE_DIRTY_SAMPLER_STATES_GS);
+
+ if (!ice->shaders.uncompiled[MESA_SHADER_TESS_EVAL]) {
+ /* BLORP disabled tessellation, that's fine for the next draw */
+ skip_stage_bits |= IRIS_STAGE_DIRTY_TCS |
+ IRIS_STAGE_DIRTY_TES |
+ IRIS_STAGE_DIRTY_CONSTANTS_TCS |
+ IRIS_STAGE_DIRTY_CONSTANTS_TES |
+ IRIS_STAGE_DIRTY_BINDINGS_TCS |
+ IRIS_STAGE_DIRTY_BINDINGS_TES;
+ }
+
+ if (!ice->shaders.uncompiled[MESA_SHADER_GEOMETRY]) {
+ /* BLORP disabled geometry shaders, that's fine for the next draw */
+ skip_stage_bits |= IRIS_STAGE_DIRTY_GS |
+ IRIS_STAGE_DIRTY_CONSTANTS_GS |
+ IRIS_STAGE_DIRTY_BINDINGS_GS;
}
+
+ /* we can skip flagging IRIS_DIRTY_DEPTH_BUFFER, if
+ * BLORP_BATCH_NO_EMIT_DEPTH_STENCIL is set.
+ */
+ if (blorp_batch->flags & BLORP_BATCH_NO_EMIT_DEPTH_STENCIL)
+ skip_bits |= IRIS_DIRTY_DEPTH_BUFFER;
+
+ if (!params->wm_prog_data)
+ skip_bits |= IRIS_DIRTY_BLEND_STATE | IRIS_DIRTY_PS_BLEND;
+
+ ice->state.dirty |= ~skip_bits;
+ ice->state.stage_dirty |= ~skip_stage_bits;
+
+ if (params->src.enabled)
+ iris_bo_bump_seqno(params->src.addr.buffer, batch->next_seqno,
+ IRIS_DOMAIN_OTHER_READ);
+ if (params->dst.enabled)
+ iris_bo_bump_seqno(params->dst.addr.buffer, batch->next_seqno,
+ IRIS_DOMAIN_RENDER_WRITE);
if (params->depth.enabled)
- iris_depth_cache_add_bo(batch, params->depth.addr.buffer);
+ iris_bo_bump_seqno(params->depth.addr.buffer, batch->next_seqno,
+ IRIS_DOMAIN_DEPTH_WRITE);
if (params->stencil.enabled)
- iris_depth_cache_add_bo(batch, params->stencil.addr.buffer);
+ iris_bo_bump_seqno(params->stencil.addr.buffer, batch->next_seqno,
+ IRIS_DOMAIN_DEPTH_WRITE);
}
void
blorp_init(&ice->blorp, ice, &screen->isl_dev);
ice->blorp.compiler = screen->compiler;
-
- ice->vtbl.blorp_exec = iris_blorp_exec;
+ ice->blorp.lookup_shader = iris_blorp_lookup_shader;
+ ice->blorp.upload_shader = iris_blorp_upload_shader;
+ ice->blorp.exec = iris_blorp_exec;
}
projects / mesa.git / blobdiff