lima/ppir: add ppir_node to ppir_src

[mesa.git] / src / gallium / drivers / iris / iris_bufmgr.h

diff --git a/src/gallium/drivers/iris/iris_bufmgr.h b/src/gallium/drivers/iris/iris_bufmgr.h
index 8be545cb04b4d043dc75c97f8a44eff7c0f2a920..f05a71edf982b008e62eb66b604151572a2f8bc1 100644 (file)
--- a/src/gallium/drivers/iris/iris_bufmgr.h
+++ b/src/gallium/drivers/iris/iris_bufmgr.h
@@ -48,14 +48,11 @@ struct pipe_debug_callback;
  *
  * We lay out the virtual address space as follows:
  *
- * - [0,   4K): Nothing  (empty page for null address)
- * - [4K,  4G): Shaders  (Instruction Base Address)
- * - [4G,  8G): Surfaces (Surface State Base Address, Bindless ...)
- * - [8G, 12G): Dynamic  (Dynamic State Base Address)
- * - [12G, *):  Other    (everything else in the full 48-bit VMA)
- *
- * A special 64kB "binder" buffer lives at the start of the surface memory
- * zone, holding binding tables referring to objects in the rest of the zone.
+ * - [0,   4K): Nothing            (empty page for null address)
+ * - [4K,  4G): Shaders            (Instruction Base Address)
+ * - [4G,  8G): Surfaces & Binders (Surface State Base Address, Bindless ...)
+ * - [8G, 12G): Dynamic            (Dynamic State Base Address)
+ * - [12G, *):  Other              (everything else in the full 48-bit VMA)
  *
  * A special buffer for border color lives at the start of the dynamic state
  * memory zone.  This unfortunately has to be handled specially because the
@@ -65,32 +62,29 @@ struct pipe_debug_callback;
  * each a separate VMA.  However, we assign address globally, so buffers will
  * have the same address in all GEM contexts.  This lets us have a single BO
  * field for the address, which is easy and cheap.
- *
- * One exception is the special "binder" BO.  Binders are context-local,
- * so while there are many of them, all binders are stored at the same
- * fixed address (in different VMAs).
  */
 enum iris_memory_zone {
    IRIS_MEMZONE_SHADER,
+   IRIS_MEMZONE_BINDER,
    IRIS_MEMZONE_SURFACE,
    IRIS_MEMZONE_DYNAMIC,
    IRIS_MEMZONE_OTHER,
 
-   IRIS_MEMZONE_BINDER,
    IRIS_MEMZONE_BORDER_COLOR_POOL,
 };
 
 /* Intentionally exclude single buffer "zones" */
-#define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 2)
+#define IRIS_MEMZONE_COUNT (IRIS_MEMZONE_OTHER + 1)
+
+#define IRIS_BINDER_SIZE (64 * 1024)
+#define IRIS_MAX_BINDERS 100
 
 #define IRIS_MEMZONE_SHADER_START     (0ull * (1ull << 32))
-#define IRIS_MEMZONE_SURFACE_START    (1ull * (1ull << 32))
+#define IRIS_MEMZONE_BINDER_START     (1ull * (1ull << 32))
+#define IRIS_MEMZONE_SURFACE_START    (IRIS_MEMZONE_BINDER_START + IRIS_MAX_BINDERS * IRIS_BINDER_SIZE)
 #define IRIS_MEMZONE_DYNAMIC_START    (2ull * (1ull << 32))
 #define IRIS_MEMZONE_OTHER_START      (3ull * (1ull << 32))
 
-#define IRIS_BINDER_ADDRESS IRIS_MEMZONE_SURFACE_START
-#define IRIS_BINDER_SIZE (64 * 1024)
-
 #define IRIS_BORDER_COLOR_POOL_ADDRESS IRIS_MEMZONE_DYNAMIC_START
 #define IRIS_BORDER_COLOR_POOL_SIZE (64 * 1024)
 
@@ -125,6 +119,10 @@ struct iris_bo {
     * It should not be considered authoritative, but can be used to avoid a
     * linear walk of the validation list in the common case by guessing that
     * exec_bos[bo->index] == bo and confirming whether that's the case.
+    *
+    * XXX: this is not ideal now that we have more than one batch per context,
+    * XXX: as the index will flop back and forth between the render index and
+    * XXX: compute index...
     */
    unsigned index;
 
@@ -193,6 +191,7 @@ struct iris_bo {
 };
 
 #define BO_ALLOC_ZEROED     (1<<0)
+#define BO_ALLOC_COHERENT   (1<<1)
 
 /**
  * Allocate a buffer object.
@@ -220,10 +219,11 @@ struct iris_bo *iris_bo_alloc(struct iris_bufmgr *bufmgr,
 struct iris_bo *iris_bo_alloc_tiled(struct iris_bufmgr *bufmgr,
                                     const char *name,
                                     uint64_t size,
+                                    uint32_t alignment,
+                                    enum iris_memory_zone memzone,
                                     uint32_t tiling_mode,
                                     uint32_t pitch,
-                                    unsigned flags,
-                                    enum iris_memory_zone memzone);
+                                    unsigned flags);
 
 struct iris_bo *
 iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
@@ -252,6 +252,9 @@ void iris_bo_unreference(struct iris_bo *bo);
 #define MAP_INTERNAL_MASK (0xff << 24)
 #define MAP_RAW           (0x01 << 24)
 
+#define MAP_FLAGS         (MAP_READ | MAP_WRITE | MAP_ASYNC | \
+                           MAP_PERSISTENT | MAP_COHERENT | MAP_INTERNAL_MASK)
+
 /**
  * Maps the buffer into userspace.
  *
@@ -329,6 +332,7 @@ void iris_bufmgr_enable_reuse(struct iris_bufmgr *bufmgr);
 int iris_bo_wait(struct iris_bo *bo, int64_t timeout_ns);
 
 uint32_t iris_create_hw_context(struct iris_bufmgr *bufmgr);
+uint32_t iris_clone_hw_context(struct iris_bufmgr *bufmgr, uint32_t ctx_id);
 
 #define IRIS_CONTEXT_LOW_PRIORITY    ((I915_CONTEXT_MIN_USER_PRIORITY-1)/2)
 #define IRIS_CONTEXT_MEDIUM_PRIORITY (I915_CONTEXT_DEFAULT_PRIORITY)
@@ -365,4 +369,6 @@ iris_bo_offset_from_base_address(struct iris_bo *bo)
    return bo->gtt_offset;
 }
 
+enum iris_memory_zone iris_memzone_for_address(uint64_t address);
+
 #endif /* IRIS_BUFMGR_H */