#include "intel/common/gen_debug.h"
#include "intel/compiler/brw_compiler.h"
#include "iris_batch.h"
+#include "iris_binder.h"
+#include "iris_fence.h"
#include "iris_resource.h"
#include "iris_screen.h"
struct blorp_batch;
struct blorp_params;
+#define IRIS_MAX_TEXTURE_BUFFER_SIZE (1 << 27)
#define IRIS_MAX_TEXTURE_SAMPLERS 32
/* IRIS_MAX_ABOS and IRIS_MAX_SSBOS must be the same. */
#define IRIS_MAX_ABOS 16
#define IRIS_MAX_SSBOS 16
#define IRIS_MAX_VIEWPORTS 16
+#define IRIS_MAX_CLIP_PLANES 8
+
+enum iris_param_domain {
+ BRW_PARAM_DOMAIN_BUILTIN = 0,
+ BRW_PARAM_DOMAIN_IMAGE,
+};
+
+#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
+#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
+#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
+#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
+#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
+#define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
/**
* Dirty flags. When state changes, we flag some combination of these
#define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
#define IRIS_DIRTY_CONSTANTS_GS (1ull << 38)
#define IRIS_DIRTY_CONSTANTS_FS (1ull << 39)
-#define IRIS_DIRTY_DEPTH_BUFFER (1ull << 40)
-#define IRIS_DIRTY_WM (1ull << 41)
-#define IRIS_DIRTY_BINDINGS_VS (1ull << 42)
-#define IRIS_DIRTY_BINDINGS_TCS (1ull << 43)
-#define IRIS_DIRTY_BINDINGS_TES (1ull << 44)
-#define IRIS_DIRTY_BINDINGS_GS (1ull << 45)
-#define IRIS_DIRTY_BINDINGS_FS (1ull << 46)
-#define IRIS_DIRTY_BINDINGS_CS (1ull << 47)
-#define IRIS_DIRTY_SO_BUFFERS (1ull << 48)
-#define IRIS_DIRTY_SO_DECL_LIST (1ull << 49)
-#define IRIS_DIRTY_STREAMOUT (1ull << 50)
-#define IRIS_DIRTY_VF_SGVS (1ull << 51)
+#define IRIS_DIRTY_CONSTANTS_CS (1ull << 40)
+#define IRIS_DIRTY_DEPTH_BUFFER (1ull << 41)
+#define IRIS_DIRTY_WM (1ull << 42)
+#define IRIS_DIRTY_BINDINGS_VS (1ull << 43)
+#define IRIS_DIRTY_BINDINGS_TCS (1ull << 44)
+#define IRIS_DIRTY_BINDINGS_TES (1ull << 45)
+#define IRIS_DIRTY_BINDINGS_GS (1ull << 46)
+#define IRIS_DIRTY_BINDINGS_FS (1ull << 47)
+#define IRIS_DIRTY_BINDINGS_CS (1ull << 48)
+#define IRIS_DIRTY_SO_BUFFERS (1ull << 49)
+#define IRIS_DIRTY_SO_DECL_LIST (1ull << 50)
+#define IRIS_DIRTY_STREAMOUT (1ull << 51)
+#define IRIS_DIRTY_VF_SGVS (1ull << 52)
+#define IRIS_DIRTY_VF (1ull << 53)
+#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
+
+#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
+ IRIS_DIRTY_SAMPLER_STATES_CS | \
+ IRIS_DIRTY_UNCOMPILED_CS | \
+ IRIS_DIRTY_CONSTANTS_CS | \
+ IRIS_DIRTY_BINDINGS_CS)
+
+#define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
+
+#define IRIS_ALL_DIRTY_BINDINGS (IRIS_DIRTY_BINDINGS_VS | \
+ IRIS_DIRTY_BINDINGS_TCS | \
+ IRIS_DIRTY_BINDINGS_TES | \
+ IRIS_DIRTY_BINDINGS_GS | \
+ IRIS_DIRTY_BINDINGS_FS | \
+ IRIS_DIRTY_BINDINGS_CS)
/**
* Non-orthogonal state (NOS) dependency flags.
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
PIPE_CONTROL_INSTRUCTION_INVALIDATE)
+enum iris_predicate_state {
+ /* The first two states are used if we can determine whether to draw
+ * without having to look at the values in the query object buffer. This
+ * will happen if there is no conditional render in progress, if the query
+ * object is already completed or if something else has already added
+ * samples to the preliminary result.
+ */
+ IRIS_PREDICATE_STATE_RENDER,
+ IRIS_PREDICATE_STATE_DONT_RENDER,
+
+ /* In this case whether to draw or not depends on the result of an
+ * MI_PREDICATE command so the predicate enable bit needs to be checked.
+ */
+ IRIS_PREDICATE_STATE_USE_BIT,
+};
+
/** @} */
/**
/** The program data (owned by the program cache hash table) */
struct brw_stage_prog_data *prog_data;
+ /** A list of system values to be uploaded as uniforms. */
+ enum brw_param_builtin *system_values;
+ unsigned num_system_values;
+
+ /** Number of constbufs expected by the shader. */
+ unsigned num_cbufs;
+
/**
* Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
* (the VUE-based information for transform feedback outputs).
* API context state that is replicated per shader stage.
*/
struct iris_shader_state {
+ /** Uniform Buffers */
struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+
+ struct pipe_constant_buffer cbuf0;
+ bool cbuf0_needs_upload;
+
+ /** Shader Storage Buffers */
struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
+ /** Shader Storage Images (image load store) */
+ struct {
+ struct pipe_resource *res;
+ struct iris_state_ref surface_state;
+ unsigned access;
+
+ /** Gen8-only uniform data for image lowering */
+ struct brw_image_param param;
+ } image[PIPE_MAX_SHADER_IMAGES];
+
struct iris_state_ref sampler_table;
struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
- unsigned num_samplers;
- unsigned num_textures;
+
+ /** Bitfield of which image views are bound (non-null). */
+ uint32_t bound_image_views;
+
+ /** Bitfield of which sampler views are bound (non-null). */
+ uint32_t bound_sampler_views;
+};
+
+/**
+ * Gallium CSO for stream output (transform feedback) targets.
+ */
+struct iris_stream_output_target {
+ struct pipe_stream_output_target base;
+
+ /** Storage holding the offset where we're writing in the buffer */
+ struct iris_state_ref offset;
+
+ /** Stride (dwords-per-vertex) during this transform feedback operation */
+ uint16_t stride;
};
/**
struct iris_batch *batch,
struct iris_vtable *vtbl,
struct pipe_debug_callback *dbg);
+ void (*init_compute_context)(struct iris_screen *screen,
+ struct iris_batch *batch,
+ struct iris_vtable *vtbl,
+ struct pipe_debug_callback *dbg);
void (*upload_render_state)(struct iris_context *ice,
struct iris_batch *batch,
const struct pipe_draw_info *draw);
+ void (*update_surface_base_address)(struct iris_batch *batch,
+ struct iris_binder *binder);
+ void (*upload_compute_state)(struct iris_context *ice,
+ struct iris_batch *batch,
+ const struct pipe_grid_info *grid);
+ void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
+ uint32_t src);
+ void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
+ uint32_t src);
+ void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
+ uint32_t val);
+ void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
+ uint64_t val);
+ void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
+ struct iris_bo *bo, uint32_t offset);
+ void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
+ struct iris_bo *bo, uint32_t offset);
+ void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
+ struct iris_bo *bo, uint32_t offset,
+ bool predicated);
+ void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
+ struct iris_bo *bo, uint32_t offset,
+ bool predicated);
+ void (*store_data_imm32)(struct iris_batch *batch,
+ struct iris_bo *bo, uint32_t offset,
+ uint32_t value);
+ void (*store_data_imm64)(struct iris_batch *batch,
+ struct iris_bo *bo, uint32_t offset,
+ uint64_t value);
+ void (*copy_mem_mem)(struct iris_batch *batch,
+ struct iris_bo *dst_bo, uint32_t dst_offset,
+ struct iris_bo *src_bo, uint32_t src_offset,
+ unsigned bytes);
void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
struct iris_bo *bo, uint32_t offset,
uint64_t imm);
unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
- void (*store_derived_program_state)(const struct gen_device_info *devinfo,
+ void (*store_derived_program_state)(struct iris_context *ice,
enum iris_program_cache_id cache_id,
struct iris_compiled_shader *shader);
uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
const struct brw_vue_map *vue_map);
void (*populate_vs_key)(const struct iris_context *ice,
+ const struct shader_info *info,
struct brw_vs_prog_key *key);
void (*populate_tcs_key)(const struct iris_context *ice,
struct brw_tcs_prog_key *key);
struct brw_gs_prog_key *key);
void (*populate_fs_key)(const struct iris_context *ice,
struct brw_wm_prog_key *key);
+ void (*populate_cs_key)(const struct iris_context *ice,
+ struct brw_cs_prog_key *key);
};
/**
struct blorp_context blorp;
- /** The main batch for rendering. */
- struct iris_batch render_batch;
+ struct iris_batch batches[IRIS_BATCH_COUNT];
+
+ struct u_upload_mgr *query_buffer_uploader;
struct {
struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
struct hash_table *cache;
unsigned urb_size;
+
+ /**
+ * Scratch buffers for various sizes and stages.
+ *
+ * Indexed by the "Per-Thread Scratch Space" field's 4-bit encoding,
+ * and shader stage.
+ */
+ struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
} shaders;
struct {
struct pipe_scissor_state scissors[IRIS_MAX_VIEWPORTS];
struct pipe_stencil_ref stencil_ref;
struct pipe_framebuffer_state framebuffer;
+ struct pipe_clip_state clip_planes;
+
+ float default_outer_level[4];
+ float default_inner_level[2];
+
+ /** Bitfield of which vertex buffers are bound (non-null). */
+ uint64_t bound_vertex_buffers;
+
+ bool primitive_restart;
+ unsigned cut_index;
+ enum pipe_prim_type prim_mode:8;
+ uint8_t vertices_per_patch;
+
+ /** The last compute grid size */
+ uint32_t last_grid[3];
+ /** Reference to the BO containing the compute grid size */
+ struct iris_state_ref grid_size;
+ /** Reference to the SURFACE_STATE for the compute grid resource */
+ struct iris_state_ref grid_surf_state;
+
+ /** Bitfield of whether color blending is enabled for RT[i] */
+ uint8_t blend_enables;
/** Are depth writes enabled? (Depth buffer may or may not exist.) */
bool depth_writes_enabled;
struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
bool streamout_active;
+
+ bool statistics_counters_enabled;
+
+ /** Current conditional rendering mode */
+ enum iris_predicate_state predicate;
+
+ /**
+ * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
+ * render context that needs to be uploaded to the compute context.
+ */
+ struct iris_bo *compute_predicate;
+
+ /** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
+ bool prims_generated_query_active;
+
/** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
uint32_t *streamout;
+ /** Current strides for each streamout buffer */
+ uint16_t *streamout_strides;
+
/** The SURFACE_STATE for a 1x1x1 null surface. */
struct iris_state_ref unbound_tex;
// "I'm streaming this out at draw time and never want it again!"
struct u_upload_mgr *dynamic_uploader;
+ struct iris_binder binder;
+
struct iris_border_color_pool border_color_pool;
+ /** The high 16-bits of the last VBO/index buffer addresses */
+ uint16_t last_vbo_high_bits[33];
+ uint16_t last_index_bo_high_bits;
+
/**
* Resources containing streamed state which our render context
* currently points to. Used to re-add these to the validation
struct pipe_resource *color_calc;
struct pipe_resource *scissor;
struct pipe_resource *blend;
+ struct pipe_resource *index_buffer;
} last_res;
} state;
};
void iris_init_resource_functions(struct pipe_context *ctx);
void iris_init_query_functions(struct pipe_context *ctx);
void iris_update_compiled_shaders(struct iris_context *ice);
+void iris_update_compiled_compute_shader(struct iris_context *ice);
+void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
+ uint32_t *dst);
+
/* iris_blit.c */
void iris_blorp_surf_for_resource(struct blorp_surf *surf,
/* iris_draw.c */
void iris_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
+void iris_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
/* iris_pipe_control.c */
void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
uint32_t flags);
-void iris_cache_sets_clear(struct iris_batch *batch);
-void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
-void iris_cache_flush_for_render(struct iris_batch *batch,
- struct iris_bo *bo,
- enum isl_format format,
- enum isl_aux_usage aux_usage);
-void iris_render_cache_add_bo(struct iris_batch *batch,
- struct iris_bo *bo,
- enum isl_format format,
- enum isl_aux_usage aux_usage);
-void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
-void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
-
void iris_init_flush_functions(struct pipe_context *ctx);
/* iris_blorp.c */
-
+void gen8_init_blorp(struct iris_context *ice);
void gen9_init_blorp(struct iris_context *ice);
void gen10_init_blorp(struct iris_context *ice);
+void gen11_init_blorp(struct iris_context *ice);
/* iris_border_color.c */
void iris_init_border_color_pool(struct iris_context *ice);
+void iris_destroy_border_color_pool(struct iris_context *ice);
void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
uint32_t iris_upload_border_color(struct iris_context *ice,
union pipe_color_union *color);
/* iris_state.c */
-
+void gen8_init_state(struct iris_context *ice);
void gen9_init_state(struct iris_context *ice);
void gen10_init_state(struct iris_context *ice);
+void gen11_init_state(struct iris_context *ice);
/* iris_program.c */
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage);
+struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
+ unsigned per_thread_scratch,
+ gl_shader_stage stage);
/* iris_program_cache.c */
void iris_init_program_cache(struct iris_context *ice);
void iris_destroy_program_cache(struct iris_context *ice);
void iris_print_program_cache(struct iris_context *ice);
-bool iris_bind_cached_shader(struct iris_context *ice,
- enum iris_program_cache_id cache_id,
- const void *key);
-void iris_unbind_shader(struct iris_context *ice,
- enum iris_program_cache_id cache_id);
-void iris_upload_and_bind_shader(struct iris_context *ice,
- enum iris_program_cache_id cache_id,
- const void *key,
- const void *assembly,
- struct brw_stage_prog_data *prog_data,
- uint32_t *streamout);
+struct iris_compiled_shader *iris_find_cached_shader(struct iris_context *ice,
+ enum iris_program_cache_id,
+ uint32_t key_size,
+ const void *key);
+struct iris_compiled_shader *iris_upload_shader(struct iris_context *ice,
+ enum iris_program_cache_id,
+ uint32_t key_size,
+ const void *key,
+ const void *assembly,
+ struct brw_stage_prog_data *,
+ uint32_t *streamout,
+ enum brw_param_builtin *sysv,
+ unsigned num_system_values,
+ unsigned num_cbufs);
const void *iris_find_previous_compile(const struct iris_context *ice,
enum iris_program_cache_id cache_id,
unsigned program_string_id);
uint32_t *kernel_out,
void *prog_data_out);
+/* iris_query.c */
+
+void iris_math_div32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t D);
+
+uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
+ uint64_t gpu_timestamp);
+
+/* iris_resolve.c */
+
+void iris_predraw_resolve_inputs(struct iris_batch *batch,
+ struct iris_shader_state *shs);
+void iris_predraw_resolve_framebuffer(struct iris_context *ice,
+ struct iris_batch *batch);
+void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
+ struct iris_batch *batch);
+void iris_cache_sets_clear(struct iris_batch *batch);
+void iris_flush_depth_and_render_caches(struct iris_batch *batch);
+void iris_cache_flush_for_read(struct iris_batch *batch, struct iris_bo *bo);
+void iris_cache_flush_for_render(struct iris_batch *batch,
+ struct iris_bo *bo,
+ enum isl_format format,
+ enum isl_aux_usage aux_usage);
+void iris_render_cache_add_bo(struct iris_batch *batch,
+ struct iris_bo *bo,
+ enum isl_format format,
+ enum isl_aux_usage aux_usage);
+void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
+void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
+
#endif
projects / mesa.git / blobdiff