#define IRIS_MAX_ABOS 16
#define IRIS_MAX_SSBOS 16
#define IRIS_MAX_VIEWPORTS 16
+#define IRIS_MAX_CLIP_PLANES 8
+
+enum iris_param_domain {
+ BRW_PARAM_DOMAIN_BUILTIN = 0,
+ BRW_PARAM_DOMAIN_IMAGE,
+};
+
+#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
+#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
+#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
+#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
+#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
+#define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
/**
* Dirty flags. When state changes, we flag some combination of these
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | \
PIPE_CONTROL_INSTRUCTION_INVALIDATE)
+enum iris_predicate_state {
+ /* The first two states are used if we can determine whether to draw
+ * without having to look at the values in the query object buffer. This
+ * will happen if there is no conditional render in progress, if the query
+ * object is already completed or if something else has already added
+ * samples to the preliminary result.
+ */
+ IRIS_PREDICATE_STATE_RENDER,
+ IRIS_PREDICATE_STATE_DONT_RENDER,
+
+ /* In this case whether to draw or not depends on the result of an
+ * MI_PREDICATE command so the predicate enable bit needs to be checked.
+ */
+ IRIS_PREDICATE_STATE_USE_BIT,
+};
+
/** @} */
/**
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ /** Number of constbufs expected by the shader. */
+ unsigned num_cbufs;
+
/**
* Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
* (the VUE-based information for transform feedback outputs).
struct pipe_resource *res;
struct iris_state_ref surface_state;
unsigned access;
+
+ /** Gen8-only uniform data for image lowering */
+ struct brw_image_param param;
} image[PIPE_MAX_SHADER_IMAGES];
struct iris_state_ref sampler_table;
struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
- unsigned num_images;
- unsigned num_samplers;
- unsigned num_textures;
+
+ /** Bitfield of which image views are bound (non-null). */
+ uint32_t bound_image_views;
+
+ /** Bitfield of which sampler views are bound (non-null). */
+ uint32_t bound_sampler_views;
+};
+
+/**
+ * Gallium CSO for stream output (transform feedback) targets.
+ */
+struct iris_stream_output_target {
+ struct pipe_stream_output_target base;
+
+ /** Storage holding the offset where we're writing in the buffer */
+ struct iris_state_ref offset;
+
+ /** Stride (dwords-per-vertex) during this transform feedback operation */
+ uint16_t stride;
};
/**
void (*upload_compute_state)(struct iris_context *ice,
struct iris_batch *batch,
const struct pipe_grid_info *grid);
- void (*load_register_reg32)(struct iris_batch *batch, uint32_t src,
- uint32_t dst);
- void (*load_register_reg64)(struct iris_batch *batch, uint32_t src,
- uint32_t dst);
+ void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
+ uint32_t src);
+ void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
+ uint32_t src);
void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
uint32_t val);
void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
struct iris_batch batches[IRIS_BATCH_COUNT];
+ struct u_upload_mgr *query_buffer_uploader;
+
struct {
struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
float default_outer_level[4];
float default_inner_level[2];
+ /** Bitfield of which vertex buffers are bound (non-null). */
+ uint64_t bound_vertex_buffers;
+
bool primitive_restart;
unsigned cut_index;
enum pipe_prim_type prim_mode:8;
/** Reference to the SURFACE_STATE for the compute grid resource */
struct iris_state_ref grid_surf_state;
+ /**
+ * Array of aux usages for drawing, altered to account for any
+ * self-dependencies from resources bound for sampling and rendering.
+ */
+ enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
+
+ /** Bitfield of whether color blending is enabled for RT[i] */
+ uint8_t blend_enables;
+
/** Are depth writes enabled? (Depth buffer may or may not exist.) */
bool depth_writes_enabled;
bool statistics_counters_enabled;
+ /** Current conditional rendering mode */
+ enum iris_predicate_state predicate;
+
+ /**
+ * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
+ * render context that needs to be uploaded to the compute context.
+ */
+ struct iris_bo *compute_predicate;
+
/** Is a PIPE_QUERY_PRIMITIVES_GENERATED query active? */
bool prims_generated_query_active;
/** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
uint32_t *streamout;
+ /** Current strides for each streamout buffer */
+ uint16_t *streamout_strides;
+
/** The SURFACE_STATE for a 1x1x1 null surface. */
struct iris_state_ref unbound_tex;
void iris_init_flush_functions(struct pipe_context *ctx);
/* iris_blorp.c */
-
+void gen8_init_blorp(struct iris_context *ice);
void gen9_init_blorp(struct iris_context *ice);
void gen10_init_blorp(struct iris_context *ice);
void gen11_init_blorp(struct iris_context *ice);
/* iris_border_color.c */
void iris_init_border_color_pool(struct iris_context *ice);
+void iris_destroy_border_color_pool(struct iris_context *ice);
void iris_border_color_pool_reserve(struct iris_context *ice, unsigned count);
uint32_t iris_upload_border_color(struct iris_context *ice,
union pipe_color_union *color);
/* iris_state.c */
-
+void gen8_init_state(struct iris_context *ice);
void gen9_init_state(struct iris_context *ice);
void gen10_init_state(struct iris_context *ice);
void gen11_init_state(struct iris_context *ice);
/* iris_program.c */
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage);
-unsigned iris_get_shader_num_ubos(const struct iris_context *ice,
- gl_shader_stage stage);
-uint32_t iris_get_scratch_space(struct iris_context *ice,
- unsigned per_thread_scratch,
- gl_shader_stage stage);
+struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
+ unsigned per_thread_scratch,
+ gl_shader_stage stage);
/* iris_program_cache.c */
struct brw_stage_prog_data *,
uint32_t *streamout,
enum brw_param_builtin *sysv,
- unsigned num_system_values);
+ unsigned num_system_values,
+ unsigned num_cbufs);
const void *iris_find_previous_compile(const struct iris_context *ice,
enum iris_program_cache_id cache_id,
unsigned program_string_id);
/* iris_query.c */
+void iris_math_div32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t D);
+
uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
uint64_t gpu_timestamp);
/* iris_resolve.c */
void iris_predraw_resolve_inputs(struct iris_context *ice,
- struct iris_batch *batch);
+ struct iris_batch *batch,
+ struct iris_shader_state *shs,
+ bool *draw_aux_buffer_disabled);
void iris_predraw_resolve_framebuffer(struct iris_context *ice,
- struct iris_batch *batch);
+ struct iris_batch *batch,
+ bool *draw_aux_buffer_disabled);
void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
struct iris_batch *batch);
void iris_cache_sets_clear(struct iris_batch *batch);
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