#include "pipe/p_context.h"
#include "pipe/p_state.h"
+#include "util/slab.h"
#include "util/u_debug.h"
#include "intel/blorp/blorp.h"
-#include "intel/common/gen_debug.h"
+#include "intel/dev/gen_debug.h"
+#include "intel/common/gen_l3_config.h"
#include "intel/compiler/brw_compiler.h"
#include "iris_batch.h"
#include "iris_binder.h"
BRW_PARAM_DOMAIN_IMAGE,
};
+enum {
+ DRI_CONF_BO_REUSE_DISABLED,
+ DRI_CONF_BO_REUSE_ALL
+};
+
#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
#define IRIS_DIRTY_FS (1ull << 32)
#define IRIS_DIRTY_CS (1ull << 33)
#define IRIS_DIRTY_URB (1ull << 34)
+#define IRIS_SHIFT_FOR_DIRTY_CONSTANTS 35
#define IRIS_DIRTY_CONSTANTS_VS (1ull << 35)
#define IRIS_DIRTY_CONSTANTS_TCS (1ull << 36)
#define IRIS_DIRTY_CONSTANTS_TES (1ull << 37)
#define IRIS_DIRTY_VF_SGVS (1ull << 52)
#define IRIS_DIRTY_VF (1ull << 53)
#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
+#define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55)
+#define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
+#define IRIS_DIRTY_VF_STATISTICS (1ull << 57)
+#define IRIS_DIRTY_PMA_FIX (1ull << 58)
+#define IRIS_DIRTY_DEPTH_BOUNDS (1ull << 59)
+#define IRIS_DIRTY_RENDER_BUFFER (1ull << 60)
#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
IRIS_DIRTY_SAMPLER_STATES_CS | \
IRIS_DIRTY_UNCOMPILED_CS | \
IRIS_DIRTY_CONSTANTS_CS | \
- IRIS_DIRTY_BINDINGS_CS)
+ IRIS_DIRTY_BINDINGS_CS | \
+ IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
#define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
IRIS_DIRTY_BINDINGS_TES | \
IRIS_DIRTY_BINDINGS_GS | \
IRIS_DIRTY_BINDINGS_FS | \
- IRIS_DIRTY_BINDINGS_CS)
+ IRIS_DIRTY_BINDINGS_CS | \
+ IRIS_DIRTY_RENDER_BUFFER)
/**
* Non-orthogonal state (NOS) dependency flags.
IRIS_NOS_COUNT,
};
+/** @{
+ *
+ * Program cache keys for state based recompiles.
+ */
+
+struct iris_base_prog_key {
+ unsigned program_string_id;
+};
+
+struct iris_vue_prog_key {
+ struct iris_base_prog_key base;
+
+ unsigned nr_userclip_plane_consts:4;
+};
+
+struct iris_vs_prog_key {
+ struct iris_vue_prog_key vue;
+};
+
+struct iris_tcs_prog_key {
+ struct iris_vue_prog_key vue;
+
+ uint16_t tes_primitive_mode;
+
+ uint8_t input_vertices;
+
+ bool quads_workaround;
+
+ /** A bitfield of per-patch outputs written. */
+ uint32_t patch_outputs_written;
+
+ /** A bitfield of per-vertex outputs written. */
+ uint64_t outputs_written;
+};
+
+struct iris_tes_prog_key {
+ struct iris_vue_prog_key vue;
+
+ /** A bitfield of per-patch inputs read. */
+ uint32_t patch_inputs_read;
+
+ /** A bitfield of per-vertex inputs read. */
+ uint64_t inputs_read;
+};
+
+struct iris_gs_prog_key {
+ struct iris_vue_prog_key vue;
+};
+
+struct iris_fs_prog_key {
+ struct iris_base_prog_key base;
+
+ unsigned nr_color_regions:5;
+ bool flat_shade:1;
+ bool alpha_test_replicate_alpha:1;
+ bool alpha_to_coverage:1;
+ bool clamp_fragment_color:1;
+ bool persample_interp:1;
+ bool multisample_fbo:1;
+ bool force_dual_color_blend:1;
+ bool coherent_fb_fetch:1;
+
+ uint8_t color_outputs_valid;
+ uint64_t input_slots_valid;
+};
+
+struct iris_cs_prog_key {
+ struct iris_base_prog_key base;
+};
+
+/** @} */
+
struct iris_depth_stencil_alpha_state;
/**
PIPE_CONTROL_STATE_CACHE_INVALIDATE = (1 << 22),
PIPE_CONTROL_STALL_AT_SCOREBOARD = (1 << 23),
PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24),
+ PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25),
+ PIPE_CONTROL_FLUSH_HDC = (1 << 26),
};
#define PIPE_CONTROL_CACHE_FLUSH_BITS \
/** @} */
+/**
+ * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
+ * It primarily contains the NIR for the shader.
+ *
+ * Each API-facing shader can be compiled into multiple shader variants,
+ * based on non-orthogonal state dependencies, recorded in the shader key.
+ *
+ * See iris_compiled_shader, which represents a compiled shader variant.
+ */
+struct iris_uncompiled_shader {
+ struct nir_shader *nir;
+
+ struct pipe_stream_output_info stream_output;
+
+ /* A SHA1 of the serialized NIR for the disk cache. */
+ unsigned char nir_sha1[20];
+
+ unsigned program_id;
+
+ /** Bitfield of (1 << IRIS_NOS_*) flags. */
+ unsigned nos;
+
+ /** Have any shader variants been compiled yet? */
+ bool compiled_once;
+
+ /** Should we use ALT mode for math? Useful for ARB programs. */
+ bool use_alt_mode;
+
+ bool needs_edge_flag;
+
+ /* Whether shader uses atomic operations. */
+ bool uses_atomic_load_store;
+
+ /** Constant data scraped from the shader by nir_opt_large_constants */
+ struct pipe_resource *const_data;
+
+ /** Surface state for const_data */
+ struct iris_state_ref const_data_state;
+};
+
+enum iris_surface_group {
+ IRIS_SURFACE_GROUP_RENDER_TARGET,
+ IRIS_SURFACE_GROUP_RENDER_TARGET_READ,
+ IRIS_SURFACE_GROUP_CS_WORK_GROUPS,
+ IRIS_SURFACE_GROUP_TEXTURE,
+ IRIS_SURFACE_GROUP_IMAGE,
+ IRIS_SURFACE_GROUP_UBO,
+ IRIS_SURFACE_GROUP_SSBO,
+
+ IRIS_SURFACE_GROUP_COUNT,
+};
+
+enum {
+ /* Invalid value for a binding table index. */
+ IRIS_SURFACE_NOT_USED = 0xa0a0a0a0,
+};
+
+struct iris_binding_table {
+ uint32_t size_bytes;
+
+ /** Number of surfaces in each group, before compacting. */
+ uint32_t sizes[IRIS_SURFACE_GROUP_COUNT];
+
+ /** Initial offset of each group. */
+ uint32_t offsets[IRIS_SURFACE_GROUP_COUNT];
+
+ /** Mask of surfaces used in each group. */
+ uint64_t used_mask[IRIS_SURFACE_GROUP_COUNT];
+};
+
/**
* A compiled shader variant, containing a pointer to the GPU assembly,
* as well as program data and other packets needed by state upload.
*/
uint32_t *streamout;
+ struct iris_binding_table bt;
+
/**
* Shader packets and other data derived from prog_data. These must be
* completely determined from prog_data.
uint8_t derived_data[0];
};
-/**
- * Constant buffer (UBO) information. See iris_set_const_buffer().
- */
-struct iris_const_buffer {
- /** The resource and offset for the actual constant data */
- struct iris_state_ref data;
-
- /** The resource and offset for the SURFACE_STATE for pull access. */
- struct iris_state_ref surface_state;
-};
-
/**
* API context state that is replicated per shader stage.
*/
struct iris_shader_state {
/** Uniform Buffers */
- struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+ struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+ struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
- struct pipe_constant_buffer cbuf0;
- bool cbuf0_needs_upload;
+ bool sysvals_need_upload;
/** Shader Storage Buffers */
- struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
- struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
+ struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
+ struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
/** Shader Storage Images (image load store) */
- struct {
- struct pipe_resource *res;
- struct iris_state_ref surface_state;
- unsigned access;
-
- /** Gen8-only uniform data for image lowering */
- struct brw_image_param param;
- } image[PIPE_MAX_SHADER_IMAGES];
+ struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
struct iris_state_ref sampler_table;
struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
+ /** Bitfield of which constant buffers are bound (non-null). */
+ uint32_t bound_cbufs;
+
/** Bitfield of which image views are bound (non-null). */
uint32_t bound_image_views;
/** Bitfield of which sampler views are bound (non-null). */
uint32_t bound_sampler_views;
+
+ /** Bitfield of which shader storage buffers are bound (non-null). */
+ uint32_t bound_ssbos;
+
+ /** Bitfield of which shader storage buffers are writable. */
+ uint32_t writable_ssbos;
};
/**
/** Storage holding the offset where we're writing in the buffer */
struct iris_state_ref offset;
- /** Stride (dwords-per-vertex) during this transform feedback operation */
+ /** Stride (bytes-per-vertex) during this transform feedback operation */
uint16_t stride;
-};
-/**
- * Virtual table for generation-specific (genxml) function calls.
- */
-struct iris_vtable {
- void (*destroy_state)(struct iris_context *ice);
- void (*init_render_context)(struct iris_screen *screen,
- struct iris_batch *batch,
- struct iris_vtable *vtbl,
- struct pipe_debug_callback *dbg);
- void (*init_compute_context)(struct iris_screen *screen,
- struct iris_batch *batch,
- struct iris_vtable *vtbl,
- struct pipe_debug_callback *dbg);
- void (*upload_render_state)(struct iris_context *ice,
- struct iris_batch *batch,
- const struct pipe_draw_info *draw);
- void (*update_surface_base_address)(struct iris_batch *batch,
- struct iris_binder *binder);
- void (*upload_compute_state)(struct iris_context *ice,
- struct iris_batch *batch,
- const struct pipe_grid_info *grid);
- void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
- uint32_t src);
- void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
- uint32_t src);
- void (*load_register_imm32)(struct iris_batch *batch, uint32_t reg,
- uint32_t val);
- void (*load_register_imm64)(struct iris_batch *batch, uint32_t reg,
- uint64_t val);
- void (*load_register_mem32)(struct iris_batch *batch, uint32_t reg,
- struct iris_bo *bo, uint32_t offset);
- void (*load_register_mem64)(struct iris_batch *batch, uint32_t reg,
- struct iris_bo *bo, uint32_t offset);
- void (*store_register_mem32)(struct iris_batch *batch, uint32_t reg,
- struct iris_bo *bo, uint32_t offset,
- bool predicated);
- void (*store_register_mem64)(struct iris_batch *batch, uint32_t reg,
- struct iris_bo *bo, uint32_t offset,
- bool predicated);
- void (*store_data_imm32)(struct iris_batch *batch,
- struct iris_bo *bo, uint32_t offset,
- uint32_t value);
- void (*store_data_imm64)(struct iris_batch *batch,
- struct iris_bo *bo, uint32_t offset,
- uint64_t value);
- void (*copy_mem_mem)(struct iris_batch *batch,
- struct iris_bo *dst_bo, uint32_t dst_offset,
- struct iris_bo *src_bo, uint32_t src_offset,
- unsigned bytes);
- void (*emit_raw_pipe_control)(struct iris_batch *batch, uint32_t flags,
- struct iris_bo *bo, uint32_t offset,
- uint64_t imm);
-
- unsigned (*derived_program_state_size)(enum iris_program_cache_id id);
- void (*store_derived_program_state)(struct iris_context *ice,
- enum iris_program_cache_id cache_id,
- struct iris_compiled_shader *shader);
- uint32_t *(*create_so_decl_list)(const struct pipe_stream_output_info *sol,
- const struct brw_vue_map *vue_map);
- void (*populate_vs_key)(const struct iris_context *ice,
- const struct shader_info *info,
- struct brw_vs_prog_key *key);
- void (*populate_tcs_key)(const struct iris_context *ice,
- struct brw_tcs_prog_key *key);
- void (*populate_tes_key)(const struct iris_context *ice,
- struct brw_tes_prog_key *key);
- void (*populate_gs_key)(const struct iris_context *ice,
- struct brw_gs_prog_key *key);
- void (*populate_fs_key)(const struct iris_context *ice,
- struct brw_wm_prog_key *key);
- void (*populate_cs_key)(const struct iris_context *ice,
- struct brw_cs_prog_key *key);
+ /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
+ bool zeroed;
};
/**
/** A debug callback for KHR_debug output. */
struct pipe_debug_callback dbg;
+ /** A device reset status callback for notifying that the GPU is hosed. */
+ struct pipe_device_reset_callback reset;
+
/** Slab allocator for iris_transfer_map objects. */
struct slab_child_pool transfer_pool;
- struct iris_vtable vtbl;
-
struct blorp_context blorp;
struct iris_batch batches[IRIS_BATCH_COUNT];
int baseinstance;
} params;
+ /**
+ * Are the above values the ones stored in the draw_params buffer?
+ * If so, we can compare them against new values to see if anything
+ * changed. If not, we need to assume they changed.
+ */
+ bool params_valid;
+
/**
* Resource and offset that stores draw_parameters from the indirect
* buffer or to the buffer that stures the previous values for non
* indirect draws.
*/
- struct pipe_resource *draw_params_res;
- uint32_t draw_params_offset;
+ struct iris_state_ref draw_params;
struct {
/**
* contains parameters that are not present in the indirect buffer as
* drawid and is_indexed_draw. They will go in their own vertex element.
*/
- struct pipe_resource *derived_draw_params_res;
- uint32_t derived_draw_params_offset;
-
- bool is_indirect;
+ struct iris_state_ref derived_draw_params;
} draw;
struct {
struct u_upload_mgr *uploader;
struct hash_table *cache;
- unsigned urb_size;
+ /** Is a GS or TES outputting points or lines? */
+ bool output_topology_is_points_or_lines;
/**
* Scratch buffers for various sizes and stages.
struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
} shaders;
+ struct {
+ struct iris_query *query;
+ bool condition;
+ } condition;
+
+ struct gen_perf_context *perf_ctx;
+
+ /** Frame number for debug prints */
+ uint32_t frame;
+
struct {
uint64_t dirty;
uint64_t dirty_for_nos[IRIS_NOS_COUNT];
bool primitive_restart;
unsigned cut_index;
enum pipe_prim_type prim_mode:8;
+ bool prim_is_points_or_lines;
uint8_t vertices_per_patch;
+ bool window_space_position;
+
/** The last compute grid size */
uint32_t last_grid[3];
/** Reference to the BO containing the compute grid size */
*/
enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
+ enum gen_urb_deref_block_size urb_deref_block_size;
+
/** Bitfield of whether color blending is enabled for RT[i] */
uint8_t blend_enables;
/** Do vertex shader uses edge flag ? */
bool vs_needs_edge_flag;
- /** Do any samplers (for any stage) need border color? */
- bool need_border_colors;
+ /** Do any samplers need border color? One bit per shader stage. */
+ uint8_t need_border_colors;
struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
bool streamout_active;
enum iris_predicate_state predicate;
/**
- * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
+ * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
* render context that needs to be uploaded to the compute context.
*/
struct iris_bo *compute_predicate;
/** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
uint32_t *streamout;
- /** Current strides for each streamout buffer */
- uint16_t *streamout_strides;
-
/** The SURFACE_STATE for a 1x1x1 null surface. */
struct iris_state_ref unbound_tex;
struct iris_state_ref null_fb;
struct u_upload_mgr *surface_uploader;
- // XXX: may want a separate uploader for "hey I made a CSO!" vs
- // "I'm streaming this out at draw time and never want it again!"
struct u_upload_mgr *dynamic_uploader;
struct iris_binder binder;
struct pipe_resource *scissor;
struct pipe_resource *blend;
struct pipe_resource *index_buffer;
+ struct pipe_resource *cs_thread_ids;
+ struct pipe_resource *cs_desc;
} last_res;
+
+ /** Records the size of variable-length state for INTEL_DEBUG=bat */
+ struct hash_table_u64 *sizes;
+
+ /** Last rendering scale argument provided to genX(emit_hashing_mode). */
+ unsigned current_hash_scale;
} state;
};
struct pipe_context *
iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
+void iris_lost_context_state(struct iris_batch *batch);
+
void iris_init_blit_functions(struct pipe_context *ctx);
void iris_init_clear_functions(struct pipe_context *ctx);
void iris_init_program_functions(struct pipe_context *ctx);
void iris_init_resource_functions(struct pipe_context *ctx);
-void iris_init_query_functions(struct pipe_context *ctx);
+void iris_init_perfquery_functions(struct pipe_context *ctx);
void iris_update_compiled_shaders(struct iris_context *ice);
void iris_update_compiled_compute_shader(struct iris_context *ice);
void iris_fill_cs_push_const_buffer(struct brw_cs_prog_data *cs_prog_data,
+ unsigned threads,
uint32_t *dst);
/* iris_blit.c */
-void iris_blorp_surf_for_resource(struct blorp_surf *surf,
+void iris_blorp_surf_for_resource(struct isl_device *isl_dev,
+ struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
unsigned level,
bool is_render_target);
+void iris_copy_region(struct blorp_context *blorp,
+ struct iris_batch *batch,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box);
/* iris_draw.c */
/* iris_pipe_control.c */
void iris_emit_pipe_control_flush(struct iris_batch *batch,
- uint32_t flags);
-void iris_emit_pipe_control_write(struct iris_batch *batch, uint32_t flags,
+ const char *reason, uint32_t flags);
+void iris_emit_pipe_control_write(struct iris_batch *batch,
+ const char *reason, uint32_t flags,
struct iris_bo *bo, uint32_t offset,
uint64_t imm);
void iris_emit_end_of_pipe_sync(struct iris_batch *batch,
- uint32_t flags);
+ const char *reason, uint32_t flags);
+void iris_flush_all_caches(struct iris_batch *batch);
-void iris_init_flush_functions(struct pipe_context *ctx);
+#define iris_handle_always_flush_cache(batch) \
+ if (unlikely(batch->screen->driconf.always_flush_cache)) \
+ iris_flush_all_caches(batch);
-/* iris_blorp.c */
-void gen8_init_blorp(struct iris_context *ice);
-void gen9_init_blorp(struct iris_context *ice);
-void gen10_init_blorp(struct iris_context *ice);
-void gen11_init_blorp(struct iris_context *ice);
+void iris_init_flush_functions(struct pipe_context *ctx);
/* iris_border_color.c */
uint32_t iris_upload_border_color(struct iris_context *ice,
union pipe_color_union *color);
-/* iris_state.c */
-void gen8_init_state(struct iris_context *ice);
-void gen9_init_state(struct iris_context *ice);
-void gen10_init_state(struct iris_context *ice);
-void gen11_init_state(struct iris_context *ice);
-
/* iris_program.c */
+void iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
+ struct pipe_shader_buffer *buf,
+ struct iris_state_ref *surf_state,
+ bool ssbo);
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage);
struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
unsigned per_thread_scratch,
gl_shader_stage stage);
+uint32_t iris_group_index_to_bti(const struct iris_binding_table *bt,
+ enum iris_surface_group group,
+ uint32_t index);
+uint32_t iris_bti_to_group_index(const struct iris_binding_table *bt,
+ enum iris_surface_group group,
+ uint32_t bti);
+
+/* iris_disk_cache.c */
+
+void iris_disk_cache_store(struct disk_cache *cache,
+ const struct iris_uncompiled_shader *ish,
+ const struct iris_compiled_shader *shader,
+ const void *prog_key,
+ uint32_t prog_key_size);
+struct iris_compiled_shader *
+iris_disk_cache_retrieve(struct iris_context *ice,
+ const struct iris_uncompiled_shader *ish,
+ const void *prog_key,
+ uint32_t prog_key_size);
/* iris_program_cache.c */
uint32_t *streamout,
enum brw_param_builtin *sysv,
unsigned num_system_values,
- unsigned num_cbufs);
+ unsigned num_cbufs,
+ const struct iris_binding_table *bt);
const void *iris_find_previous_compile(const struct iris_context *ice,
enum iris_program_cache_id cache_id,
unsigned program_string_id);
uint32_t key_size,
uint32_t *kernel_out,
void *prog_data_out);
-bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
+bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch, uint32_t stage,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
uint32_t *kernel_out,
void *prog_data_out);
-/* iris_query.c */
-
-void iris_math_div32_gpr0(struct iris_context *ice,
- struct iris_batch *batch,
- uint32_t D);
-
-uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
- uint64_t gpu_timestamp);
-
/* iris_resolve.c */
void iris_predraw_resolve_inputs(struct iris_context *ice,
struct iris_batch *batch,
- struct iris_shader_state *shs,
bool *draw_aux_buffer_disabled,
+ gl_shader_stage stage,
bool consider_framebuffer);
void iris_predraw_resolve_framebuffer(struct iris_context *ice,
struct iris_batch *batch,
enum isl_aux_usage aux_usage);
void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
+int iris_get_driver_query_info(struct pipe_screen *pscreen, unsigned index,
+ struct pipe_driver_query_info *info);
+int iris_get_driver_query_group_info(struct pipe_screen *pscreen,
+ unsigned index,
+ struct pipe_driver_query_group_info *info);
+
+/* iris_state.c */
+void gen9_toggle_preemption(struct iris_context *ice,
+ struct iris_batch *batch,
+ const struct pipe_draw_info *draw);
+
+
+
+#ifdef genX
+# include "iris_genx_protos.h"
+#else
+# define genX(x) gen4_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen5_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen6_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen7_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen75_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen8_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen9_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen10_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen11_##x
+# include "iris_genx_protos.h"
+# undef genX
+# define genX(x) gen12_##x
+# include "iris_genx_protos.h"
+# undef genX
+#endif
#endif
projects / mesa.git / blobdiff