#include "pipe/p_state.h"
#include "util/u_debug.h"
#include "intel/blorp/blorp.h"
-#include "intel/common/gen_debug.h"
+#include "intel/dev/gen_debug.h"
#include "intel/compiler/brw_compiler.h"
#include "iris_batch.h"
#include "iris_binder.h"
#define IRIS_MAX_ABOS 16
#define IRIS_MAX_SSBOS 16
#define IRIS_MAX_VIEWPORTS 16
+#define IRIS_MAX_CLIP_PLANES 8
+
+enum iris_param_domain {
+ BRW_PARAM_DOMAIN_BUILTIN = 0,
+ BRW_PARAM_DOMAIN_IMAGE,
+};
+
+#define BRW_PARAM(domain, val) (BRW_PARAM_DOMAIN_##domain << 24 | (val))
+#define BRW_PARAM_DOMAIN(param) ((uint32_t)(param) >> 24)
+#define BRW_PARAM_VALUE(param) ((uint32_t)(param) & 0x00ffffff)
+#define BRW_PARAM_IMAGE(idx, offset) BRW_PARAM(IMAGE, ((idx) << 8) | (offset))
+#define BRW_PARAM_IMAGE_IDX(value) (BRW_PARAM_VALUE(value) >> 8)
+#define BRW_PARAM_IMAGE_OFFSET(value)(BRW_PARAM_VALUE(value) & 0xf)
/**
* Dirty flags. When state changes, we flag some combination of these
#define IRIS_DIRTY_VF_SGVS (1ull << 52)
#define IRIS_DIRTY_VF (1ull << 53)
#define IRIS_DIRTY_VF_TOPOLOGY (1ull << 54)
+#define IRIS_DIRTY_RENDER_RESOLVES_AND_FLUSHES (1ull << 55)
+#define IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES (1ull << 56)
+#define IRIS_DIRTY_VF_STATISTICS (1ull << 57)
#define IRIS_ALL_DIRTY_FOR_COMPUTE (IRIS_DIRTY_CS | \
IRIS_DIRTY_SAMPLER_STATES_CS | \
IRIS_DIRTY_UNCOMPILED_CS | \
IRIS_DIRTY_CONSTANTS_CS | \
- IRIS_DIRTY_BINDINGS_CS)
+ IRIS_DIRTY_BINDINGS_CS | \
+ IRIS_DIRTY_COMPUTE_RESOLVES_AND_FLUSHES)
#define IRIS_ALL_DIRTY_FOR_RENDER ~IRIS_ALL_DIRTY_FOR_COMPUTE
/** @} */
+/**
+ * An uncompiled, API-facing shader. This is the Gallium CSO for shaders.
+ * It primarily contains the NIR for the shader.
+ *
+ * Each API-facing shader can be compiled into multiple shader variants,
+ * based on non-orthogonal state dependencies, recorded in the shader key.
+ *
+ * See iris_compiled_shader, which represents a compiled shader variant.
+ */
+struct iris_uncompiled_shader {
+ struct nir_shader *nir;
+
+ struct pipe_stream_output_info stream_output;
+
+ /* The serialized NIR (for the disk cache) and size in bytes. */
+ void *ir_cache_binary;
+ uint32_t ir_cache_binary_size;
+
+ unsigned program_id;
+
+ /** Bitfield of (1 << IRIS_NOS_*) flags. */
+ unsigned nos;
+
+ /** Have any shader variants been compiled yet? */
+ bool compiled_once;
+};
+
/**
* A compiled shader variant, containing a pointer to the GPU assembly,
* as well as program data and other packets needed by state upload.
enum brw_param_builtin *system_values;
unsigned num_system_values;
+ /** Number of constbufs expected by the shader. */
+ unsigned num_cbufs;
+
/**
* Derived 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets
* (the VUE-based information for transform feedback outputs).
uint8_t derived_data[0];
};
-/**
- * Constant buffer (UBO) information. See iris_set_const_buffer().
- */
-struct iris_const_buffer {
- /** The resource and offset for the actual constant data */
- struct iris_state_ref data;
-
- /** The resource and offset for the SURFACE_STATE for pull access. */
- struct iris_state_ref surface_state;
-};
-
/**
* API context state that is replicated per shader stage.
*/
struct iris_shader_state {
/** Uniform Buffers */
- struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+ struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+ struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
struct pipe_constant_buffer cbuf0;
bool cbuf0_needs_upload;
/** Shader Storage Buffers */
- struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
- struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
+ struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
+ struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
/** Shader Storage Images (image load store) */
- struct {
- struct pipe_resource *res;
- struct iris_state_ref surface_state;
- unsigned access;
- } image[PIPE_MAX_SHADER_IMAGES];
+ struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
struct iris_state_ref sampler_table;
struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
+ /** Bitfield of which constant buffers are bound (non-null). */
+ uint32_t bound_cbufs;
+
/** Bitfield of which image views are bound (non-null). */
uint32_t bound_image_views;
/** Bitfield of which sampler views are bound (non-null). */
uint32_t bound_sampler_views;
+
+ /** Bitfield of which shader storage buffers are bound (non-null). */
+ uint32_t bound_ssbos;
+
+ /** Bitfield of which shader storage buffers are writable. */
+ uint32_t writable_ssbos;
};
/**
/** Storage holding the offset where we're writing in the buffer */
struct iris_state_ref offset;
+
+ /** Stride (dwords-per-vertex) during this transform feedback operation */
+ uint16_t stride;
+
+ /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
+ bool zeroed;
};
/**
void (*upload_compute_state)(struct iris_context *ice,
struct iris_batch *batch,
const struct pipe_grid_info *grid);
+ void (*rebind_buffer)(struct iris_context *ice,
+ struct iris_resource *res,
+ uint64_t old_address);
void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
uint32_t src);
void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
struct brw_wm_prog_key *key);
void (*populate_cs_key)(const struct iris_context *ice,
struct brw_cs_prog_key *key);
+ uint32_t (*mocs)(const struct iris_bo *bo);
};
/**
/** A debug callback for KHR_debug output. */
struct pipe_debug_callback dbg;
+ /** A device reset status callback for notifying that the GPU is hosed. */
+ struct pipe_device_reset_callback reset;
+
/** Slab allocator for iris_transfer_map objects. */
struct slab_child_pool transfer_pool;
struct iris_batch batches[IRIS_BATCH_COUNT];
+ struct u_upload_mgr *query_buffer_uploader;
+
+ struct {
+ struct {
+ /**
+ * Either the value of BaseVertex for indexed draw calls or the value
+ * of the argument <first> for non-indexed draw calls.
+ */
+ int firstvertex;
+ int baseinstance;
+ } params;
+
+ /**
+ * Resource and offset that stores draw_parameters from the indirect
+ * buffer or to the buffer that stures the previous values for non
+ * indirect draws.
+ */
+ struct pipe_resource *draw_params_res;
+ uint32_t draw_params_offset;
+
+ struct {
+ /**
+ * The value of DrawID. This always comes in from it's own vertex
+ * buffer since it's not part of the indirect draw parameters.
+ */
+ int drawid;
+
+ /**
+ * Stores if an indexed or non-indexed draw (~0/0). Useful to
+ * calculate BaseVertex as an AND of firstvertex and is_indexed_draw.
+ */
+ int is_indexed_draw;
+ } derived_params;
+
+ /**
+ * Resource and offset used for GL_ARB_shader_draw_parameters which
+ * contains parameters that are not present in the indirect buffer as
+ * drawid and is_indexed_draw. They will go in their own vertex element.
+ */
+ struct pipe_resource *derived_draw_params_res;
+ uint32_t derived_draw_params_offset;
+
+ bool is_indirect;
+ } draw;
+
struct {
struct iris_uncompiled_shader *uncompiled[MESA_SHADER_STAGES];
struct iris_compiled_shader *prog[MESA_SHADER_STAGES];
unsigned urb_size;
+ /** Is a GS or TES outputting points or lines? */
+ bool output_topology_is_points_or_lines;
+
+ /* Track last VS URB entry size */
+ unsigned last_vs_entry_size;
+
/**
* Scratch buffers for various sizes and stages.
*
struct iris_bo *scratch_bos[1 << 4][MESA_SHADER_STAGES];
} shaders;
+ struct {
+ struct iris_query *query;
+ bool condition;
+ } condition;
+
struct {
uint64_t dirty;
uint64_t dirty_for_nos[IRIS_NOS_COUNT];
bool primitive_restart;
unsigned cut_index;
enum pipe_prim_type prim_mode:8;
+ bool prim_is_points_or_lines;
uint8_t vertices_per_patch;
/** The last compute grid size */
/** Reference to the SURFACE_STATE for the compute grid resource */
struct iris_state_ref grid_surf_state;
+ /**
+ * Array of aux usages for drawing, altered to account for any
+ * self-dependencies from resources bound for sampling and rendering.
+ */
+ enum isl_aux_usage draw_aux_usage[BRW_MAX_DRAW_BUFFERS];
+
+ /** Bitfield of whether color blending is enabled for RT[i] */
+ uint8_t blend_enables;
+
/** Are depth writes enabled? (Depth buffer may or may not exist.) */
bool depth_writes_enabled;
struct iris_shader_state shaders[MESA_SHADER_STAGES];
- /** Do any samplers (for any stage) need border color? */
- bool need_border_colors;
+ /** Do vertex shader uses shader draw parameters ? */
+ bool vs_uses_draw_params;
+ bool vs_uses_derived_draw_params;
+ bool vs_needs_sgvs_element;
+
+ /** Do vertex shader uses edge flag ? */
+ bool vs_needs_edge_flag;
+
+ /** Do any samplers need border color? One bit per shader stage. */
+ uint8_t need_border_colors;
struct pipe_stream_output_target *so_target[PIPE_MAX_SO_BUFFERS];
bool streamout_active;
enum iris_predicate_state predicate;
/**
- * Query BO with a MI_PREDICATE_DATA snapshot calculated on the
+ * Query BO with a MI_PREDICATE_RESULT snapshot calculated on the
* render context that needs to be uploaded to the compute context.
*/
struct iris_bo *compute_predicate;
/** 3DSTATE_STREAMOUT and 3DSTATE_SO_DECL_LIST packets */
uint32_t *streamout;
+ /** Current strides for each streamout buffer */
+ uint16_t *streamout_strides;
+
/** The SURFACE_STATE for a 1x1x1 null surface. */
struct iris_state_ref unbound_tex;
struct pipe_context *
iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
+void iris_lost_context_state(struct iris_batch *batch);
+
void iris_init_blit_functions(struct pipe_context *ctx);
void iris_init_clear_functions(struct pipe_context *ctx);
void iris_init_program_functions(struct pipe_context *ctx);
/* iris_blit.c */
-void iris_blorp_surf_for_resource(struct blorp_surf *surf,
+void iris_blorp_surf_for_resource(struct iris_vtable *vtbl,
+ struct blorp_surf *surf,
struct pipe_resource *p_res,
enum isl_aux_usage aux_usage,
+ unsigned level,
bool is_render_target);
+void iris_copy_region(struct blorp_context *blorp,
+ struct iris_batch *batch,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box);
/* iris_draw.c */
void iris_init_flush_functions(struct pipe_context *ctx);
/* iris_blorp.c */
-
+void gen8_init_blorp(struct iris_context *ice);
void gen9_init_blorp(struct iris_context *ice);
void gen10_init_blorp(struct iris_context *ice);
void gen11_init_blorp(struct iris_context *ice);
union pipe_color_union *color);
/* iris_state.c */
-
+void gen8_init_state(struct iris_context *ice);
void gen9_init_state(struct iris_context *ice);
void gen10_init_state(struct iris_context *ice);
void gen11_init_state(struct iris_context *ice);
+void gen8_emit_urb_setup(struct iris_context *ice,
+ struct iris_batch *batch,
+ const unsigned size[4],
+ bool tess_present, bool gs_present);
+void gen9_emit_urb_setup(struct iris_context *ice,
+ struct iris_batch *batch,
+ const unsigned size[4],
+ bool tess_present, bool gs_present);
+void gen10_emit_urb_setup(struct iris_context *ice,
+ struct iris_batch *batch,
+ const unsigned size[4],
+ bool tess_present, bool gs_present);
+void gen11_emit_urb_setup(struct iris_context *ice,
+ struct iris_batch *batch,
+ const unsigned size[4],
+ bool tess_present, bool gs_present);
/* iris_program.c */
const struct shader_info *iris_get_shader_info(const struct iris_context *ice,
gl_shader_stage stage);
-unsigned iris_get_shader_num_ubos(const struct iris_context *ice,
- gl_shader_stage stage);
-uint32_t iris_get_scratch_space(struct iris_context *ice,
- unsigned per_thread_scratch,
- gl_shader_stage stage);
+struct iris_bo *iris_get_scratch_space(struct iris_context *ice,
+ unsigned per_thread_scratch,
+ gl_shader_stage stage);
/* iris_program_cache.c */
struct brw_stage_prog_data *,
uint32_t *streamout,
enum brw_param_builtin *sysv,
- unsigned num_system_values);
+ unsigned num_system_values,
+ unsigned num_cbufs);
const void *iris_find_previous_compile(const struct iris_context *ice,
enum iris_program_cache_id cache_id,
unsigned program_string_id);
/* iris_query.c */
+void iris_math_div32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t D);
+void iris_math_add32_gpr0(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t x);
+
uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
uint64_t gpu_timestamp);
+void iris_resolve_conditional_render(struct iris_context *ice);
/* iris_resolve.c */
void iris_predraw_resolve_inputs(struct iris_context *ice,
- struct iris_batch *batch);
+ struct iris_batch *batch,
+ bool *draw_aux_buffer_disabled,
+ gl_shader_stage stage,
+ bool consider_framebuffer);
void iris_predraw_resolve_framebuffer(struct iris_context *ice,
- struct iris_batch *batch);
+ struct iris_batch *batch,
+ bool *draw_aux_buffer_disabled);
void iris_postdraw_update_resolve_tracking(struct iris_context *ice,
struct iris_batch *batch);
void iris_cache_sets_clear(struct iris_batch *batch);
void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
+/* iris_state.c */
+void gen9_toggle_preemption(struct iris_context *ice,
+ struct iris_batch *batch,
+ const struct pipe_draw_info *draw);
#endif
projects / mesa.git / blobdiff