iris: Hook up device reset callbacks

[mesa.git] / src / gallium / drivers / iris / iris_context.h

diff --git a/src/gallium/drivers/iris/iris_context.h b/src/gallium/drivers/iris/iris_context.h
index 4465eef40dd6f8c2d6d0a91a9269fd7338506e02..b6d44d637a64a04a56b041c3f1c43c1688b5c277 100644 (file)
--- a/src/gallium/drivers/iris/iris_context.h
+++ b/src/gallium/drivers/iris/iris_context.h
@@ -283,50 +283,42 @@ struct iris_compiled_shader {
    uint8_t derived_data[0];
 };
 
-/**
- * Constant buffer (UBO) information.  See iris_set_const_buffer().
- */
-struct iris_const_buffer {
-   /** The resource and offset for the actual constant data */
-   struct iris_state_ref data;
-
-   /** The resource and offset for the SURFACE_STATE for pull access. */
-   struct iris_state_ref surface_state;
-};
-
 /**
  * API context state that is replicated per shader stage.
  */
 struct iris_shader_state {
    /** Uniform Buffers */
-   struct iris_const_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+   struct pipe_shader_buffer constbuf[PIPE_MAX_CONSTANT_BUFFERS];
+   struct iris_state_ref constbuf_surf_state[PIPE_MAX_CONSTANT_BUFFERS];
 
    struct pipe_constant_buffer cbuf0;
    bool cbuf0_needs_upload;
 
    /** Shader Storage Buffers */
-   struct pipe_resource *ssbo[PIPE_MAX_SHADER_BUFFERS];
-   struct iris_state_ref ssbo_surface_state[PIPE_MAX_SHADER_BUFFERS];
+   struct pipe_shader_buffer ssbo[PIPE_MAX_SHADER_BUFFERS];
+   struct iris_state_ref ssbo_surf_state[PIPE_MAX_SHADER_BUFFERS];
 
    /** Shader Storage Images (image load store) */
-   struct {
-      struct pipe_resource *res;
-      struct iris_state_ref surface_state;
-      unsigned access;
-
-      /** Gen8-only uniform data for image lowering */
-      struct brw_image_param param;
-   } image[PIPE_MAX_SHADER_IMAGES];
+   struct iris_image_view image[PIPE_MAX_SHADER_IMAGES];
 
    struct iris_state_ref sampler_table;
    struct iris_sampler_state *samplers[IRIS_MAX_TEXTURE_SAMPLERS];
    struct iris_sampler_view *textures[IRIS_MAX_TEXTURE_SAMPLERS];
 
+   /** Bitfield of which constant buffers are bound (non-null). */
+   uint32_t bound_cbufs;
+
    /** Bitfield of which image views are bound (non-null). */
    uint32_t bound_image_views;
 
    /** Bitfield of which sampler views are bound (non-null). */
    uint32_t bound_sampler_views;
+
+   /** Bitfield of which shader storage buffers are bound (non-null). */
+   uint32_t bound_ssbos;
+
+   /** Bitfield of which shader storage buffers are writable. */
+   uint32_t writable_ssbos;
 };
 
 /**
@@ -340,6 +332,9 @@ struct iris_stream_output_target {
 
    /** Stride (dwords-per-vertex) during this transform feedback operation */
    uint16_t stride;
+
+   /** Has 3DSTATE_SO_BUFFER actually been emitted, zeroing the offsets? */
+   bool zeroed;
 };
 
 /**
@@ -363,6 +358,9 @@ struct iris_vtable {
    void (*upload_compute_state)(struct iris_context *ice,
                                 struct iris_batch *batch,
                                 const struct pipe_grid_info *grid);
+   void (*rebind_buffer)(struct iris_context *ice,
+                         struct iris_resource *res,
+                         uint64_t old_address);
    void (*load_register_reg32)(struct iris_batch *batch, uint32_t dst,
                                uint32_t src);
    void (*load_register_reg64)(struct iris_batch *batch, uint32_t dst,
@@ -442,6 +440,9 @@ struct iris_context {
    /** A debug callback for KHR_debug output. */
    struct pipe_debug_callback dbg;
 
+   /** A device reset status callback for notifying that the GPU is hosed. */
+   struct pipe_device_reset_callback reset;
+
    /** Slab allocator for iris_transfer_map objects. */
    struct slab_child_pool transfer_pool;
 
@@ -506,6 +507,9 @@ struct iris_context {
 
       unsigned urb_size;
 
+      /** Is a GS or TES outputting points or lines? */
+      bool output_topology_is_points_or_lines;
+
       /* Track last VS URB entry size */
       unsigned last_vs_entry_size;
 
@@ -550,6 +554,7 @@ struct iris_context {
       bool primitive_restart;
       unsigned cut_index;
       enum pipe_prim_type prim_mode:8;
+      bool prim_is_points_or_lines;
       uint8_t vertices_per_patch;
 
       /** The last compute grid size */
@@ -660,6 +665,8 @@ double get_time(void);
 struct pipe_context *
 iris_create_context(struct pipe_screen *screen, void *priv, unsigned flags);
 
+void iris_lost_context_state(struct iris_batch *batch);
+
 void iris_init_blit_functions(struct pipe_context *ctx);
 void iris_init_clear_functions(struct pipe_context *ctx);
 void iris_init_program_functions(struct pipe_context *ctx);
@@ -787,6 +794,9 @@ bool iris_blorp_upload_shader(struct blorp_batch *blorp_batch,
 void iris_math_div32_gpr0(struct iris_context *ice,
                           struct iris_batch *batch,
                           uint32_t D);
+void iris_math_add32_gpr0(struct iris_context *ice,
+                          struct iris_batch *batch,
+                          uint32_t x);
 
 uint64_t iris_timebase_scale(const struct gen_device_info *devinfo,
                              uint64_t gpu_timestamp);
@@ -818,4 +828,8 @@ void iris_render_cache_add_bo(struct iris_batch *batch,
 void iris_cache_flush_for_depth(struct iris_batch *batch, struct iris_bo *bo);
 void iris_depth_cache_add_bo(struct iris_batch *batch, struct iris_bo *bo);
 
+/* iris_state.c */
+void gen9_toggle_preemption(struct iris_context *ice,
+                            struct iris_batch *batch,
+                            const struct pipe_draw_info *draw);
 #endif