return;
}
- const struct util_format_description *desc =
- util_format_description(res->format);
-
- if (util_format_has_depth(desc)) {
+ if (res->format != PIPE_FORMAT_S8_UINT) {
*out_z = (void *) res;
*out_s = (void *) iris_resource_get_separate_stencil(res);
} else {
- assert(util_format_has_stencil(desc));
*out_z = NULL;
*out_s = (void *) res;
}
}
+void
+iris_resource_disable_aux(struct iris_resource *res)
+{
+ iris_bo_unreference(res->aux.bo);
+ free(res->aux.state);
+
+ // XXX: clear color BO
+
+ res->aux.usage = ISL_AUX_USAGE_NONE;
+ res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
+ res->aux.surf.size_B = 0;
+ res->aux.bo = NULL;
+ res->aux.state = NULL;
+}
+
static void
iris_resource_destroy(struct pipe_screen *screen,
struct pipe_resource *resource)
{
struct iris_resource *res = (struct iris_resource *)resource;
+ iris_resource_disable_aux(res);
+
iris_bo_unreference(res->bo);
free(res);
}
res->base.screen = pscreen;
pipe_reference_init(&res->base.reference, 1);
+ res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
+
return res;
}
+unsigned
+iris_get_num_logical_layers(const struct iris_resource *res, unsigned level)
+{
+ if (res->surf.dim == ISL_SURF_DIM_3D)
+ return minify(res->surf.logical_level0_px.depth, level);
+ else
+ return res->surf.logical_level0_px.array_len;
+}
+
+static enum isl_aux_state **
+create_aux_state_map(struct iris_resource *res, enum isl_aux_state initial)
+{
+ uint32_t total_slices = 0;
+ for (uint32_t level = 0; level < res->surf.levels; level++)
+ total_slices += iris_get_num_logical_layers(res, level);
+
+ const size_t per_level_array_size =
+ res->surf.levels * sizeof(enum isl_aux_state *);
+
+ /* We're going to allocate a single chunk of data for both the per-level
+ * reference array and the arrays of aux_state. This makes cleanup
+ * significantly easier.
+ */
+ const size_t total_size =
+ per_level_array_size + total_slices * sizeof(enum isl_aux_state);
+
+ void *data = malloc(total_size);
+ if (!data)
+ return NULL;
+
+ enum isl_aux_state **per_level_arr = data;
+ enum isl_aux_state *s = data + per_level_array_size;
+ for (uint32_t level = 0; level < res->surf.levels; level++) {
+ per_level_arr[level] = s;
+ const unsigned level_layers = iris_get_num_logical_layers(res, level);
+ for (uint32_t a = 0; a < level_layers; a++)
+ *(s++) = initial;
+ }
+ assert((void *)s == data + total_size);
+
+ return per_level_arr;
+}
+
+/**
+ * Allocate the initial aux surface for a resource based on aux.usage
+ */
+static bool
+iris_resource_alloc_aux(struct iris_screen *screen, struct iris_resource *res)
+{
+ struct isl_device *isl_dev = &screen->isl_dev;
+ enum isl_aux_state initial_state;
+ UNUSED bool ok = false;
+ uint8_t memset_value = 0;
+ uint32_t alloc_flags = 0;
+
+ assert(!res->aux.bo);
+
+ switch (res->aux.usage) {
+ case ISL_AUX_USAGE_NONE:
+ res->aux.surf.size_B = 0;
+ break;
+ case ISL_AUX_USAGE_HIZ:
+ initial_state = ISL_AUX_STATE_AUX_INVALID;
+ memset_value = 0;
+ ok = isl_surf_get_hiz_surf(isl_dev, &res->surf, &res->aux.surf);
+ break;
+ case ISL_AUX_USAGE_MCS:
+ /* The Ivybridge PRM, Vol 2 Part 1 p326 says:
+ *
+ * "When MCS buffer is enabled and bound to MSRT, it is required
+ * that it is cleared prior to any rendering."
+ *
+ * Since we only use the MCS buffer for rendering, we just clear it
+ * immediately on allocation. The clear value for MCS buffers is all
+ * 1's, so we simply memset it to 0xff.
+ */
+ initial_state = ISL_AUX_STATE_CLEAR;
+ memset_value = 0xFF;
+ ok = isl_surf_get_mcs_surf(isl_dev, &res->surf, &res->aux.surf);
+ break;
+ case ISL_AUX_USAGE_CCS_D:
+ case ISL_AUX_USAGE_CCS_E:
+ /* When CCS_E is used, we need to ensure that the CCS starts off in
+ * a valid state. From the Sky Lake PRM, "MCS Buffer for Render
+ * Target(s)":
+ *
+ * "If Software wants to enable Color Compression without Fast
+ * clear, Software needs to initialize MCS with zeros."
+ *
+ * A CCS value of 0 indicates that the corresponding block is in the
+ * pass-through state which is what we want.
+ *
+ * For CCS_D, do the same thing. On Gen9+, this avoids having any
+ * undefined bits in the aux buffer.
+ */
+ initial_state = ISL_AUX_STATE_PASS_THROUGH;
+ alloc_flags |= BO_ALLOC_ZEROED;
+ ok = isl_surf_get_ccs_surf(isl_dev, &res->surf, &res->aux.surf, 0);
+ break;
+ }
+
+ /* No work is needed for a zero-sized auxiliary buffer. */
+ if (res->aux.surf.size_B == 0)
+ return true;
+
+ /* Assert that ISL gave us a valid aux surf */
+ assert(ok);
+
+ /* Create the aux_state for the auxiliary buffer. */
+ res->aux.state = create_aux_state_map(res, initial_state);
+ if (!res->aux.state)
+ return false;
+
+ /* Allocate the auxiliary buffer. ISL has stricter set of alignment rules
+ * the drm allocator. Therefore, one can pass the ISL dimensions in terms
+ * of bytes instead of trying to recalculate based on different format
+ * block sizes.
+ */
+ res->aux.bo = iris_bo_alloc_tiled(screen->bufmgr, "aux buffer",
+ res->aux.surf.size_B,
+ IRIS_MEMZONE_OTHER, I915_TILING_Y,
+ res->aux.surf.row_pitch_B, alloc_flags);
+ if (!res->aux.bo) {
+ iris_resource_disable_aux(res);
+ return false;
+ }
+
+ /* Optionally, initialize the auxiliary data to the desired value. */
+ if (memset_value != 0) {
+ void *map = iris_bo_map(NULL, res->aux.bo, MAP_WRITE | MAP_RAW);
+ if (!map) {
+ iris_resource_disable_aux(res);
+ return false;
+ }
+
+ memset(map, memset_value, res->aux.surf.size_B);
+ iris_bo_unmap(res->aux.bo);
+ }
+
+ if (res->aux.usage == ISL_AUX_USAGE_HIZ) {
+ for (unsigned level = 0; level < res->surf.levels; ++level) {
+ uint32_t width = u_minify(res->surf.phys_level0_sa.width, level);
+ uint32_t height = u_minify(res->surf.phys_level0_sa.height, level);
+
+ /* Disable HiZ for LOD > 0 unless the width/height are 8x4 aligned.
+ * For LOD == 0, we can grow the dimensions to make it work.
+ */
+ if (level == 0 || ((width & 7) == 0 && (height & 3) == 0))
+ res->aux.has_hiz |= 1 << level;
+ }
+ }
+
+ return true;
+}
+
+static bool
+supports_mcs(const struct isl_surf *surf)
+{
+ /* MCS compression only applies to multisampled resources. */
+ if (surf->samples <= 1)
+ return false;
+
+ /* See isl_surf_get_mcs_surf for details. */
+ if (surf->samples == 16 && surf->logical_level0_px.width > 8192)
+ return false;
+
+ /* Depth and stencil buffers use the IMS (interleaved) layout. */
+ if (isl_surf_usage_is_depth_or_stencil(surf->usage))
+ return false;
+
+ return true;
+}
+
+static bool
+supports_ccs(const struct gen_device_info *devinfo,
+ const struct isl_surf *surf)
+{
+ /* Gen9+ only supports CCS for Y-tiled buffers. */
+ if (surf->tiling != ISL_TILING_Y0)
+ return false;
+
+ /* CCS only supports singlesampled resources. */
+ if (surf->samples > 1)
+ return false;
+
+ /* The PRM doesn't say this explicitly, but fast-clears don't appear to
+ * work for 3D textures until Gen9 where the layout of 3D textures changes
+ * to match 2D array textures.
+ */
+ if (devinfo->gen < 9 && surf->dim != ISL_SURF_DIM_2D)
+ return false;
+
+ /* Note: still need to check the format! */
+
+ return true;
+}
+
static struct pipe_resource *
iris_resource_create_for_buffer(struct pipe_screen *pscreen,
const struct pipe_resource *templ)
struct iris_screen *screen = (struct iris_screen *)pscreen;
struct gen_device_info *devinfo = &screen->devinfo;
struct iris_resource *res = iris_alloc_resource(pscreen, templ);
- const struct util_format_description *format_desc =
- util_format_description(templ->format);
if (!res)
return NULL;
+ const struct util_format_description *format_desc =
+ util_format_description(templ->format);
const bool has_depth = util_format_has_depth(format_desc);
uint64_t modifier =
select_best_modifier(devinfo, modifiers, modifiers_count);
isl_tiling_flags_t tiling_flags = ISL_TILING_ANY_MASK;
if (modifier != DRM_FORMAT_MOD_INVALID) {
- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(modifier);
+ res->mod_info = isl_drm_modifier_get_info(modifier);
- tiling_flags = 1 << mod_info->tiling;
+ tiling_flags = 1 << res->mod_info->tiling;
} else {
if (modifiers_count > 0) {
fprintf(stderr, "Unsupported modifier, resource creation failed.\n");
.tiling_flags = tiling_flags);
assert(isl_surf_created_successfully);
- const char *name = "miptree";
+ if (res->mod_info) {
+ res->aux.possible_usages |= 1 << res->mod_info->aux_usage;
+ } else if (res->surf.samples > 1) {
+ if (supports_mcs(&res->surf))
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_MCS;
+ } else {
+ if (has_depth) {
+ if (likely(!(INTEL_DEBUG & DEBUG_NO_HIZ)))
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_HIZ;
+ } else if (likely(!(INTEL_DEBUG & DEBUG_NO_RBC)) &&
+ supports_ccs(devinfo, &res->surf)) {
+ if (isl_format_supports_ccs_e(devinfo, res->surf.format))
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_E;
+
+ if (isl_format_supports_ccs_d(devinfo, res->surf.format))
+ res->aux.possible_usages |= 1 << ISL_AUX_USAGE_CCS_D;
+ }
+ }
+
+ // XXX: we don't actually do aux yet
+ res->aux.possible_usages = 1 << ISL_AUX_USAGE_NONE;
+ res->aux.usage = util_last_bit(res->aux.possible_usages) - 1;
+
+ const char *name = "miptree";
enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
/* These are for u_upload_mgr buffers only */
memzone,
isl_tiling_to_i915_tiling(res->surf.tiling),
res->surf.row_pitch_B, 0);
- if (!res->bo) {
- iris_resource_destroy(pscreen, &res->base);
- return NULL;
- }
+
+ if (!res->bo)
+ goto fail;
+
+ if (!iris_resource_alloc_aux(screen, res))
+ goto fail;
return &res->base;
+
+fail:
+ fprintf(stderr, "XXX: resource creation failed\n");
+ iris_resource_destroy(pscreen, &res->base);
+ return NULL;
+
}
static struct pipe_resource *
if (modifier == DRM_FORMAT_MOD_INVALID) {
modifier = tiling_to_modifier(res->bo->tiling_mode);
}
- const struct isl_drm_modifier_info *mod_info =
- isl_drm_modifier_get_info(modifier);
- assert(mod_info);
+ res->mod_info = isl_drm_modifier_get_info(modifier);
+ assert(res->mod_info);
isl_surf_usage_flags_t isl_usage = pipe_bind_to_isl_usage(templ->bind);
const struct iris_format_info fmt =
iris_format_for_usage(devinfo, templ->format, isl_usage);
+ res->internal_format = templ->format;
if (templ->target == PIPE_BUFFER) {
res->surf.tiling = ISL_TILING_LINEAR;
.min_alignment_B = 0,
.row_pitch_B = whandle->stride,
.usage = isl_usage,
- .tiling_flags = 1 << mod_info->tiling);
+ .tiling_flags = 1 << res->mod_info->tiling);
assert(res->bo->tiling_mode ==
isl_tiling_to_i915_tiling(res->surf.tiling));
+
+ // XXX: create_ccs_buf_for_image?
+ if (!iris_resource_alloc_aux(screen, res))
+ goto fail;
}
return &res->base;
struct winsys_handle *whandle,
unsigned usage)
{
+ struct iris_context *ice = (struct iris_context *)ctx;
struct iris_resource *res = (struct iris_resource *)resource;
/* If this is a buffer, stride should be 0 - no need to special case */
whandle->stride = res->surf.row_pitch_B;
- whandle->modifier = tiling_to_modifier(res->bo->tiling_mode);
+ whandle->modifier =
+ res->mod_info ? res->mod_info->modifier
+ : tiling_to_modifier(res->bo->tiling_mode);
+
+ if (ctx &&
+ (!res->mod_info || res->mod_info->aux_usage != res->aux.usage)) {
+ struct iris_batch *render_batch = &ice->batches[IRIS_BATCH_RENDER];
+ iris_resource_prepare_access(ice, render_batch, res,
+ 0, INTEL_REMAINING_LEVELS,
+ 0, INTEL_REMAINING_LAYERS,
+ ISL_AUX_USAGE_NONE, false);
+ if (res->aux.usage != ISL_AUX_USAGE_NONE) {
+ iris_resource_disable_aux(res);
+ ice->state.dirty |= IRIS_ALL_DIRTY_BINDINGS;
+ }
+ } else {
+ if (res->aux.usage != ISL_AUX_USAGE_NONE) {
+ enum isl_aux_state aux_state =
+ iris_resource_get_aux_state(res, 0, 0);
+ assert(aux_state == ISL_AUX_STATE_RESOLVED ||
+ aux_state == ISL_AUX_STATE_PASS_THROUGH);
+ }
+ }
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
(usage & PIPE_TRANSFER_MAP_DIRECTLY))
return NULL;
+ if (resource->target != PIPE_BUFFER) {
+ iris_resource_access_raw(ice, &ice->batches[IRIS_BATCH_RENDER], res,
+ level, box->z, box->depth,
+ usage & PIPE_TRANSFER_WRITE);
+ }
+
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
if (iris_batch_references(&ice->batches[i], res->bo))
struct iris_context *ice = (struct iris_context *)ctx;
struct iris_resource *res = (struct iris_resource *) xfer->resource;
-
- // XXX: don't emit flushes in both engines...? we may also need to flush
- // even if there isn't a draw yet - may still be stale data in caches...
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
- if (ice->batches[i].contains_draw) {
+ if (ice->batches[i].contains_draw ||
+ ice->batches[i].cache.render->entries) {
iris_batch_maybe_flush(&ice->batches[i], 24);
iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
}
if (map->unmap)
map->unmap(map);
- // XXX: don't emit flushes in both engines...?
for (int i = 0; i < IRIS_BATCH_COUNT; i++) {
- if (ice->batches[i].contains_draw) {
+ if (ice->batches[i].contains_draw ||
+ ice->batches[i].cache.render->entries) {
iris_batch_maybe_flush(&ice->batches[i], 24);
iris_flush_and_dirty_for_history(ice, &ice->batches[i], res);
}
projects / mesa.git / blobdiff