#include "pipe/p_state.h"
#include "util/u_inlines.h"
+#include "util/u_range.h"
#include "intel/isl/isl.h"
struct iris_batch;
/** Backing storage for the resource */
struct iris_bo *bo;
+ /** offset at which data starts in the BO */
+ uint64_t offset;
+
/**
* A bitfield of PIPE_BIND_* indicating how this resource was bound
* in the past. Only meaningful for PIPE_BUFFER; used for flushing.
*/
unsigned bind_history;
+ /**
+ * For PIPE_BUFFER resources, a range which may contain valid data.
+ *
+ * This is a conservative estimate of what part of the buffer contains
+ * valid data that we have to preserve. The rest of the buffer is
+ * considered invalid, and we can promote writes to that region to
+ * be unsynchronized writes, avoiding blit copies.
+ */
+ struct util_range valid_buffer_range;
+
/**
* Auxiliary buffer information (CCS, MCS, or HiZ).
*/
/** Offset into 'bo' where the auxiliary surface starts. */
uint32_t offset;
+ /**
+ * Fast clear color for this surface. For depth surfaces, the clear
+ * value is stored as a float32 in the red component.
+ */
+ union isl_color_value clear_color;
+
+ /** Buffer object containing the indirect clear color. */
+ struct iris_bo *clear_color_bo;
+
+ /** Offset into bo where the clear color can be found. */
+ uint64_t clear_color_offset;
+
/**
* \brief The type of auxiliary compression used by this resource.
*
*/
unsigned possible_usages;
+ /**
+ * Same as possible_usages, but only with modes supported for sampling.
+ */
+ unsigned sampler_usages;
+
/**
* \brief Maps miptree slices to their current aux state.
*
* aux state for each slice.
*/
enum isl_aux_state **state;
+
+ /**
+ * If (1 << level) is set, HiZ is enabled for that miplevel.
+ */
+ uint16_t has_hiz;
} aux;
+
+ /**
+ * For external surfaces, this is DRM format modifier that was used to
+ * create or import the surface. For internal surfaces, this will always
+ * be DRM_FORMAT_MOD_INVALID.
+ */
+ const struct isl_drm_modifier_info *mod_info;
};
/**
struct pipe_sampler_view base;
struct isl_view view;
+ union isl_color_value clear_color;
+
/* A short-cut (not a reference) to the actual resource being viewed.
* Multi-planar (or depth+stencil) images may have multiple resources
* chained together; this skips having to traverse base->texture->*.
struct iris_state_ref surface_state;
};
+/**
+ * Image view representation.
+ */
+struct iris_image_view {
+ struct pipe_image_view base;
+
+ /** The resource (BO) holding our SURFACE_STATE. */
+ struct iris_state_ref surface_state;
+};
+
/**
* Gallium CSO for surfaces (framebuffer attachments).
*
struct iris_surface {
struct pipe_surface base;
struct isl_view view;
+ struct isl_view read_view;
+ union isl_color_value clear_color;
/** The resource (BO) holding our SURFACE_STATE. */
struct iris_state_ref surface_state;
+ /** The resource (BO) holding our SURFACE_STATE for read. */
+ struct iris_state_ref surface_state_read;
};
/**
void *buffer;
void *ptr;
+ /** A linear staging resource for GPU-based copy_region transfers. */
+ struct pipe_resource *staging;
+ struct blorp_context *blorp;
+ struct iris_batch *batch;
+
+ bool dest_had_defined_contents;
+
void (*unmap)(struct iris_transfer *);
};
void iris_get_depth_stencil_resources(struct pipe_resource *res,
struct iris_resource **out_z,
struct iris_resource **out_s);
+bool iris_resource_set_clear_color(struct iris_context *ice,
+ struct iris_resource *res,
+ union isl_color_value color);
+union isl_color_value
+iris_resource_get_clear_color(const struct iris_resource *res,
+ struct iris_bo **clear_color_bo,
+ uint64_t *clear_color_offset);
void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
+void iris_dirty_for_history(struct iris_context *ice,
+ struct iris_resource *res);
+uint32_t iris_flush_bits_for_history(struct iris_resource *res);
+
void iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
- struct iris_resource *res);
+ struct iris_resource *res,
+ uint32_t extra_flags,
+ const char *reason);
unsigned iris_get_num_logical_layers(const struct iris_resource *res,
unsigned level);
#define INTEL_REMAINING_LAYERS UINT32_MAX
#define INTEL_REMAINING_LEVELS UINT32_MAX
+void
+iris_hiz_exec(struct iris_context *ice,
+ struct iris_batch *batch,
+ struct iris_resource *res,
+ unsigned int level, unsigned int start_layer,
+ unsigned int num_layers, enum isl_aux_op op,
+ bool update_clear_depth);
+
/**
* Prepare a miptree for access
*
*/
void
iris_resource_prepare_access(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
* use iris_resource_prepare_access or iris_resource_finish_write.
*/
void
-iris_resource_set_aux_state(struct iris_resource *res, uint32_t level,
+iris_resource_set_aux_state(struct iris_context *ice,
+ struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t num_layers,
enum isl_aux_state aux_state);
*/
static inline void
iris_resource_access_raw(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res,
uint32_t level, uint32_t layer,
+ uint32_t num_layers,
bool write)
{
- iris_resource_prepare_access(ice, res, level, 1, layer, 1,
+ iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
ISL_AUX_USAGE_NONE, false);
- if (write)
- iris_resource_finish_write(ice, res, level, layer, 1, ISL_AUX_USAGE_NONE);
+ if (write) {
+ iris_resource_finish_write(ice, res, level, layer, num_layers,
+ ISL_AUX_USAGE_NONE);
+ }
}
+enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
+ enum isl_tiling tiling,
+ enum pipe_texture_target target);
+enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
+uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
+ uint32_t level, uint32_t z,
+ uint32_t *tile_x, uint32_t *tile_y);
enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
const struct iris_resource *res,
enum isl_format view_fmt,
enum gen9_astc5x5_wa_tex_type);
void iris_resource_prepare_texture(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res,
enum isl_format view_format,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
enum gen9_astc5x5_wa_tex_type);
void iris_resource_prepare_image(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res);
+static inline bool
+iris_resource_unfinished_aux_import(struct iris_resource *res)
+{
+ return res->base.next != NULL && res->mod_info &&
+ res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
+}
+
+void iris_resource_finish_aux_import(struct pipe_screen *pscreen,
+ struct iris_resource *res);
+
+bool iris_has_color_unresolved(const struct iris_resource *res,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
+
void iris_resource_check_level_layer(const struct iris_resource *res,
uint32_t level, uint32_t layer);
bool iris_resource_level_has_hiz(const struct iris_resource *res,
uint32_t level);
+bool iris_has_color_unresolved(const struct iris_resource *res,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
struct iris_resource *res,
bool blend_enabled,
bool draw_aux_disabled);
void iris_resource_prepare_render(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count,
enum isl_aux_usage aux_usage);
uint32_t start_layer, uint32_t layer_count,
enum isl_aux_usage aux_usage);
void iris_resource_prepare_depth(struct iris_context *ice,
+ struct iris_batch *batch,
struct iris_resource *res, uint32_t level,
uint32_t start_layer, uint32_t layer_count);
void iris_resource_finish_depth(struct iris_context *ice,
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