*/
unsigned bind_history;
+ /**
+ * A bitfield of MESA_SHADER_* stages indicating where this resource
+ * was bound.
+ */
+ unsigned bind_stages;
+
/**
* For PIPE_BUFFER resources, a range which may contain valid data.
*
/** Offset into 'bo' where the auxiliary surface starts. */
uint32_t offset;
+ struct {
+ struct isl_surf surf;
+
+ /** Offset into 'bo' where the auxiliary surface starts. */
+ uint32_t offset;
+ } extra_aux;
+
/**
* Fast clear color for this surface. For depth surfaces, the clear
* value is stored as a float32 in the red component.
uint16_t has_hiz;
} aux;
+ /**
+ * For external surfaces, this is format that was used to create or import
+ * the surface. For internal surfaces, this will always be
+ * PIPE_FORMAT_NONE.
+ */
+ enum pipe_format external_format;
+
/**
* For external surfaces, this is DRM format modifier that was used to
* create or import the surface. For internal surfaces, this will always
uint32_t offset;
};
+/**
+ * The SURFACE_STATE descriptors for a resource.
+ */
+struct iris_surface_state {
+ /**
+ * CPU-side copy of the packed SURFACE_STATE structures, already
+ * aligned so they can be uploaded as a contiguous pile of bytes.
+ *
+ * This can be updated and re-uploaded if (e.g.) addresses need to change.
+ */
+ uint32_t *cpu;
+
+ /**
+ * How many states are there? (Each aux mode has its own state.)
+ */
+ unsigned num_states;
+
+ /**
+ * Address of the resource (res->bo->gtt_offset). Note that "Surface
+ * Base Address" may be offset from this value.
+ */
+ uint64_t bo_address;
+
+ /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
+ struct iris_state_ref ref;
+};
+
/**
* Gallium CSO for sampler views (texture views).
*
struct iris_resource *res;
/** The resource (BO) holding our SURFACE_STATE. */
- struct iris_state_ref surface_state;
+ struct iris_surface_state surface_state;
};
/**
struct pipe_image_view base;
/** The resource (BO) holding our SURFACE_STATE. */
- struct iris_state_ref surface_state;
+ struct iris_surface_state surface_state;
};
/**
struct iris_surface {
struct pipe_surface base;
struct isl_view view;
+ struct isl_view read_view;
union isl_color_value clear_color;
/** The resource (BO) holding our SURFACE_STATE. */
- struct iris_state_ref surface_state;
+ struct iris_surface_state surface_state;
+ /** The resource (BO) holding our SURFACE_STATE for read. */
+ struct iris_surface_state surface_state_read;
};
/**
struct blorp_context *blorp;
struct iris_batch *batch;
+ bool dest_had_defined_contents;
+
void (*unmap)(struct iris_transfer *);
};
enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
enum isl_tiling tiling,
enum pipe_texture_target target);
+enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
uint32_t level, uint32_t z,
uint32_t *tile_x, uint32_t *tile_y);
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
enum gen9_astc5x5_wa_tex_type);
-void iris_resource_prepare_image(struct iris_context *ice,
- struct iris_batch *batch,
- struct iris_resource *res);
static inline bool
iris_resource_unfinished_aux_import(struct iris_resource *res)
bool iris_resource_level_has_hiz(const struct iris_resource *res,
uint32_t level);
+bool iris_has_color_unresolved(const struct iris_resource *res,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
struct iris_resource *res,