v3d: compute appropriate VPM memory configuration for geometry shader workloads

[mesa.git] / src / gallium / drivers / iris / iris_resource.h

diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h
index a233d57e32b0b5d3dc3dcffbe770ba3f83d11d55..65809d8a40d4ac9b9306804141bb209789707b44 100644 (file)
--- a/src/gallium/drivers/iris/iris_resource.h
+++ b/src/gallium/drivers/iris/iris_resource.h
@@ -77,6 +77,12 @@ struct iris_resource {
     */
    unsigned bind_history;
 
+   /**
+    * A bitfield of MESA_SHADER_* stages indicating where this resource
+    * was bound.
+    */
+   unsigned bind_stages;
+
    /**
     * For PIPE_BUFFER resources, a range which may contain valid data.
     *
@@ -100,6 +106,13 @@ struct iris_resource {
       /** Offset into 'bo' where the auxiliary surface starts. */
       uint32_t offset;
 
+      struct {
+         struct isl_surf surf;
+
+         /** Offset into 'bo' where the auxiliary surface starts. */
+         uint32_t offset;
+      } extra_aux;
+
       /**
        * Fast clear color for this surface.  For depth surfaces, the clear
        * value is stored as a float32 in the red component.
@@ -149,6 +162,13 @@ struct iris_resource {
       uint16_t has_hiz;
    } aux;
 
+   /**
+    * For external surfaces, this is format that was used to create or import
+    * the surface. For internal surfaces, this will always be
+    * PIPE_FORMAT_NONE.
+    */
+   enum pipe_format external_format;
+
    /**
     * For external surfaces, this is DRM format modifier that was used to
     * create or import the surface.  For internal surfaces, this will always
@@ -166,6 +186,33 @@ struct iris_state_ref {
    uint32_t offset;
 };
 
+/**
+ * The SURFACE_STATE descriptors for a resource.
+ */
+struct iris_surface_state {
+   /**
+    * CPU-side copy of the packed SURFACE_STATE structures, already
+    * aligned so they can be uploaded as a contiguous pile of bytes.
+    *
+    * This can be updated and re-uploaded if (e.g.) addresses need to change.
+    */
+   uint32_t *cpu;
+
+   /**
+    * How many states are there?  (Each aux mode has its own state.)
+    */
+   unsigned num_states;
+
+   /**
+    * Address of the resource (res->bo->gtt_offset).  Note that "Surface
+    * Base Address" may be offset from this value.
+    */
+   uint64_t bo_address;
+
+   /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
+   struct iris_state_ref ref;
+};
+
 /**
  * Gallium CSO for sampler views (texture views).
  *
@@ -187,7 +234,7 @@ struct iris_sampler_view {
    struct iris_resource *res;
 
    /** The resource (BO) holding our SURFACE_STATE. */
-   struct iris_state_ref surface_state;
+   struct iris_surface_state surface_state;
 };
 
 /**
@@ -197,7 +244,7 @@ struct iris_image_view {
    struct pipe_image_view base;
 
    /** The resource (BO) holding our SURFACE_STATE. */
-   struct iris_state_ref surface_state;
+   struct iris_surface_state surface_state;
 };
 
 /**
@@ -209,10 +256,13 @@ struct iris_image_view {
 struct iris_surface {
    struct pipe_surface base;
    struct isl_view view;
+   struct isl_view read_view;
    union isl_color_value clear_color;
 
    /** The resource (BO) holding our SURFACE_STATE. */
-   struct iris_state_ref surface_state;
+   struct iris_surface_state surface_state;
+   /** The resource (BO) holding our SURFACE_STATE for read. */
+   struct iris_surface_state surface_state_read;
 };
 
 /**
@@ -229,6 +279,8 @@ struct iris_transfer {
    struct blorp_context *blorp;
    struct iris_batch *batch;
 
+   bool dest_had_defined_contents;
+
    void (*unmap)(struct iris_transfer *);
 };
 
@@ -392,6 +444,13 @@ iris_resource_access_raw(struct iris_context *ice,
    }
 }
 
+enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
+                                            enum isl_tiling tiling,
+                                            enum pipe_texture_target target);
+enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
+uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
+                                        uint32_t level, uint32_t z,
+                                        uint32_t *tile_x, uint32_t *tile_y);
 enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
                                                    const struct iris_resource *res,
                                                    enum isl_format view_fmt,
@@ -403,9 +462,6 @@ void iris_resource_prepare_texture(struct iris_context *ice,
                                    uint32_t start_level, uint32_t num_levels,
                                    uint32_t start_layer, uint32_t num_layers,
                                    enum gen9_astc5x5_wa_tex_type);
-void iris_resource_prepare_image(struct iris_context *ice,
-                                 struct iris_batch *batch,
-                                 struct iris_resource *res);
 
 static inline bool
 iris_resource_unfinished_aux_import(struct iris_resource *res)
@@ -426,6 +482,9 @@ void iris_resource_check_level_layer(const struct iris_resource *res,
 
 bool iris_resource_level_has_hiz(const struct iris_resource *res,
                                  uint32_t level);
+bool iris_has_color_unresolved(const struct iris_resource *res,
+                               unsigned start_level, unsigned num_levels,
+                               unsigned start_layer, unsigned num_layers);
 
 enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
                                                   struct iris_resource *res,