#include "pipe/p_state.h"
#include "util/u_inlines.h"
+#include "util/u_range.h"
#include "intel/isl/isl.h"
+#include "iris_bufmgr.h"
struct iris_batch;
struct iris_context;
+struct shader_info;
#define IRIS_MAX_MIPLEVELS 15
#define IRIS_RESOURCE_FLAG_SURFACE_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
#define IRIS_RESOURCE_FLAG_DYNAMIC_MEMZONE (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
-enum gen9_astc5x5_wa_tex_type {
- GEN9_ASTC5X5_WA_TEX_TYPE_ASTC5x5 = 1 << 0,
- GEN9_ASTC5X5_WA_TEX_TYPE_AUX = 1 << 1,
-};
-
/**
* Resources represent a GPU buffer object or image (mipmap tree).
*
/** Backing storage for the resource */
struct iris_bo *bo;
+ /** offset at which data starts in the BO */
+ uint64_t offset;
+
/**
* A bitfield of PIPE_BIND_* indicating how this resource was bound
* in the past. Only meaningful for PIPE_BUFFER; used for flushing.
*/
unsigned bind_history;
+ /**
+ * A bitfield of MESA_SHADER_* stages indicating where this resource
+ * was bound.
+ */
+ unsigned bind_stages;
+
+ /**
+ * For PIPE_BUFFER resources, a range which may contain valid data.
+ *
+ * This is a conservative estimate of what part of the buffer contains
+ * valid data that we have to preserve. The rest of the buffer is
+ * considered invalid, and we can promote writes to that region to
+ * be unsynchronized writes, avoiding blit copies.
+ */
+ struct util_range valid_buffer_range;
+
/**
* Auxiliary buffer information (CCS, MCS, or HiZ).
*/
/** Offset into 'bo' where the auxiliary surface starts. */
uint32_t offset;
+ struct {
+ struct isl_surf surf;
+
+ /** Offset into 'bo' where the auxiliary surface starts. */
+ uint32_t offset;
+ } extra_aux;
+
+ /**
+ * Fast clear color for this surface. For depth surfaces, the clear
+ * value is stored as a float32 in the red component.
+ */
+ union isl_color_value clear_color;
+
+ /** Buffer object containing the indirect clear color. */
+ struct iris_bo *clear_color_bo;
+
+ /** Offset into bo where the clear color can be found. */
+ uint64_t clear_color_offset;
+
/**
* \brief The type of auxiliary compression used by this resource.
*
*/
unsigned possible_usages;
+ /**
+ * Same as possible_usages, but only with modes supported for sampling.
+ */
+ unsigned sampler_usages;
+
/**
* \brief Maps miptree slices to their current aux state.
*
uint16_t has_hiz;
} aux;
+ /**
+ * For external surfaces, this is format that was used to create or import
+ * the surface. For internal surfaces, this will always be
+ * PIPE_FORMAT_NONE.
+ */
+ enum pipe_format external_format;
+
/**
* For external surfaces, this is DRM format modifier that was used to
* create or import the surface. For internal surfaces, this will always
uint32_t offset;
};
+/**
+ * The SURFACE_STATE descriptors for a resource.
+ */
+struct iris_surface_state {
+ /**
+ * CPU-side copy of the packed SURFACE_STATE structures, already
+ * aligned so they can be uploaded as a contiguous pile of bytes.
+ *
+ * This can be updated and re-uploaded if (e.g.) addresses need to change.
+ */
+ uint32_t *cpu;
+
+ /**
+ * How many states are there? (Each aux mode has its own state.)
+ */
+ unsigned num_states;
+
+ /**
+ * Address of the resource (res->bo->gtt_offset). Note that "Surface
+ * Base Address" may be offset from this value.
+ */
+ uint64_t bo_address;
+
+ /** A reference to the GPU buffer holding our uploaded SURFACE_STATE */
+ struct iris_state_ref ref;
+};
+
/**
* Gallium CSO for sampler views (texture views).
*
struct pipe_sampler_view base;
struct isl_view view;
+ union isl_color_value clear_color;
+
/* A short-cut (not a reference) to the actual resource being viewed.
* Multi-planar (or depth+stencil) images may have multiple resources
* chained together; this skips having to traverse base->texture->*.
struct iris_resource *res;
/** The resource (BO) holding our SURFACE_STATE. */
- struct iris_state_ref surface_state;
+ struct iris_surface_state surface_state;
+};
+
+/**
+ * Image view representation.
+ */
+struct iris_image_view {
+ struct pipe_image_view base;
+
+ /** The resource (BO) holding our SURFACE_STATE. */
+ struct iris_surface_state surface_state;
};
/**
struct iris_surface {
struct pipe_surface base;
struct isl_view view;
+ struct isl_view read_view;
+ union isl_color_value clear_color;
/** The resource (BO) holding our SURFACE_STATE. */
- struct iris_state_ref surface_state;
+ struct iris_surface_state surface_state;
+ /** The resource (BO) holding our SURFACE_STATE for read. */
+ struct iris_surface_state surface_state_read;
};
/**
struct blorp_context *blorp;
struct iris_batch *batch;
+ bool dest_had_defined_contents;
+
void (*unmap)(struct iris_transfer *);
};
return res->bo;
}
+static inline uint32_t
+iris_mocs(const struct iris_bo *bo, const struct isl_device *dev)
+{
+ return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
+}
+
struct iris_format_info iris_format_for_usage(const struct gen_device_info *,
enum pipe_format pf,
isl_surf_usage_flags_t usage);
void iris_get_depth_stencil_resources(struct pipe_resource *res,
struct iris_resource **out_z,
struct iris_resource **out_s);
+bool iris_resource_set_clear_color(struct iris_context *ice,
+ struct iris_resource *res,
+ union isl_color_value color);
+union isl_color_value
+iris_resource_get_clear_color(const struct iris_resource *res,
+ struct iris_bo **clear_color_bo,
+ uint64_t *clear_color_offset);
void iris_init_screen_resource_functions(struct pipe_screen *pscreen);
+void iris_dirty_for_history(struct iris_context *ice,
+ struct iris_resource *res);
+uint32_t iris_flush_bits_for_history(struct iris_resource *res);
+
void iris_flush_and_dirty_for_history(struct iris_context *ice,
struct iris_batch *batch,
- struct iris_resource *res);
+ struct iris_resource *res,
+ uint32_t extra_flags,
+ const char *reason);
unsigned iris_get_num_logical_layers(const struct iris_resource *res,
unsigned level);
struct iris_batch *batch,
struct iris_resource *res,
unsigned int level, unsigned int start_layer,
- unsigned int num_layers, enum isl_aux_op op);
+ unsigned int num_layers, enum isl_aux_op op,
+ bool update_clear_depth);
/**
* Prepare a miptree for access
*/
void
iris_resource_prepare_access(struct iris_context *ice,
- struct iris_batch *batch,
struct iris_resource *res,
uint32_t start_level, uint32_t num_levels,
uint32_t start_layer, uint32_t num_layers,
*/
static inline void
iris_resource_access_raw(struct iris_context *ice,
- struct iris_batch *batch,
struct iris_resource *res,
uint32_t level, uint32_t layer,
uint32_t num_layers,
bool write)
{
- iris_resource_prepare_access(ice, batch, res, level, 1, layer, num_layers,
+ iris_resource_prepare_access(ice, res, level, 1, layer, num_layers,
ISL_AUX_USAGE_NONE, false);
if (write) {
iris_resource_finish_write(ice, res, level, layer, num_layers,
}
}
+enum isl_dim_layout iris_get_isl_dim_layout(const struct gen_device_info *devinfo,
+ enum isl_tiling tiling,
+ enum pipe_texture_target target);
+enum isl_surf_dim target_to_isl_surf_dim(enum pipe_texture_target target);
+uint32_t iris_resource_get_tile_offsets(const struct iris_resource *res,
+ uint32_t level, uint32_t z,
+ uint32_t *tile_x, uint32_t *tile_y);
enum isl_aux_usage iris_resource_texture_aux_usage(struct iris_context *ice,
const struct iris_resource *res,
- enum isl_format view_fmt,
- enum gen9_astc5x5_wa_tex_type);
+ enum isl_format view_fmt);
void iris_resource_prepare_texture(struct iris_context *ice,
- struct iris_batch *batch,
struct iris_resource *res,
enum isl_format view_format,
uint32_t start_level, uint32_t num_levels,
- uint32_t start_layer, uint32_t num_layers,
- enum gen9_astc5x5_wa_tex_type);
-void iris_resource_prepare_image(struct iris_context *ice,
- struct iris_batch *batch,
- struct iris_resource *res);
+ uint32_t start_layer, uint32_t num_layers);
+
+enum isl_aux_usage iris_image_view_aux_usage(struct iris_context *ice,
+ const struct pipe_image_view *pview,
+ const struct shader_info *info);
+enum isl_format iris_image_view_get_format(struct iris_context *ice,
+ const struct pipe_image_view *img);
+
+static inline bool
+iris_resource_unfinished_aux_import(struct iris_resource *res)
+{
+ return res->base.next != NULL && res->mod_info &&
+ res->mod_info->aux_usage != ISL_AUX_USAGE_NONE;
+}
+
+void iris_resource_finish_aux_import(struct pipe_screen *pscreen,
+ struct iris_resource *res);
+
+bool iris_has_color_unresolved(const struct iris_resource *res,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
void iris_resource_check_level_layer(const struct iris_resource *res,
uint32_t level, uint32_t layer);
bool iris_resource_level_has_hiz(const struct iris_resource *res,
uint32_t level);
+bool iris_sample_with_depth_aux(const struct gen_device_info *devinfo,
+ const struct iris_resource *res);
+
+bool iris_has_color_unresolved(const struct iris_resource *res,
+ unsigned start_level, unsigned num_levels,
+ unsigned start_layer, unsigned num_layers);
+
enum isl_aux_usage iris_resource_render_aux_usage(struct iris_context *ice,
struct iris_resource *res,
enum isl_format render_fmt,
projects / mesa.git / blobdiff