#include "util/u_transfer_helper.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
+#include "util/xmlconfig.h"
#include "drm-uapi/i915_drm.h"
#include "iris_context.h"
#include "iris_defines.h"
static const char *
iris_get_vendor(struct pipe_screen *pscreen)
{
- return "Mesa Project";
+ return "Intel";
}
static const char *
iris_get_name(struct pipe_screen *pscreen)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
+ static char buf[128];
const char *chipset;
switch (screen->pci_id) {
chipset = "Unknown Intel Chipset";
break;
}
- return chipset;
+
+ snprintf(buf, sizeof(buf), "Mesa %s", chipset);
+ return buf;
}
static int
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
+ case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
case PIPE_CAP_DOUBLES:
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
- case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
+ case PIPE_CAP_DRAW_PARAMETERS:
+ case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+ case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
+ case PIPE_CAP_INVALIDATE_BUFFER:
return true;
+ case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_SHADER_STENCIL_EXPORT:
return BRW_MAX_DRAW_BUFFERS;
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 15; /* 16384x16384 */
+ return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 12; /* 2048x2048 */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
/* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
return 32;
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return IRIS_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
/* Choose a cacheline (64 bytes) so that we can safely have the CPU and
* GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
case PIPE_CAP_DEVICE_ID:
return screen->pci_id;
case PIPE_CAP_VIDEO_MEMORY:
- return 0xffffffff; // XXX: bogus
+ return INT_MAX; // XXX: bogus
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
case PIPE_CAP_MAX_VARYINGS:
return 32;
*/
return devinfo->has_llc;
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ return PIPE_CONTEXT_PRIORITY_LOW |
+ PIPE_CONTEXT_PRIORITY_MEDIUM |
+ PIPE_CONTEXT_PRIORITY_HIGH;
+
// XXX: don't hardcode 00:00:02.0 PCI here
case PIPE_CAP_PCI_GROUP:
return 0;
enum pipe_shader_type p_stage,
enum pipe_shader_cap param)
{
- struct iris_screen *screen = (struct iris_screen *)pscreen;
- struct brw_compiler *compiler = screen->compiler;
gl_shader_stage stage = stage_from_pipe(p_stage);
/* this is probably not totally correct.. but it's a start: */
void *ret)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
- struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
return 0;
}
-static bool
-iris_getparam_boolean(struct iris_screen *screen, int param)
-{
- int value = 0;
- return (iris_getparam(screen, param, &value) == 0) && value;
-}
-
static int
iris_getparam_integer(struct iris_screen *screen, int param)
{
struct pipe_debug_callback *dbg = data;
unsigned id = 0;
va_list args;
+ va_start(args, fmt);
- if (!dbg->debug_message)
- return;
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
+ va_list args_copy;
+ va_copy(args_copy, args);
+ vfprintf(stderr, fmt, args_copy);
+ va_end(args_copy);
+ }
+
+ if (dbg->debug_message) {
+ dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
+ }
- va_start(args, fmt);
- dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
va_end(args);
}
struct pipe_screen *
-iris_screen_create(int fd)
+iris_screen_create(int fd, const struct pipe_screen_config *config)
{
struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
if (!screen)
screen->devinfo.timestamp_frequency =
iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
+ if (getenv("INTEL_NO_HW") != NULL)
+ screen->no_hw = true;
+
screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
if (!screen->bufmgr)
return NULL;
brw_process_intel_debug_variable();
+ screen->driconf.dual_color_blend_by_location =
+ driQueryOptionb(config->options, "dual_color_blend_by_location");
+
screen->precompile = env_var_as_boolean("shader_precompile", true);
- bool hw_has_swizzling = false; // XXX: detect?
- isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
+ isl_device_init(&screen->isl_dev, &screen->devinfo, false);
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
screen->compiler->shader_debug_log = iris_shader_debug_log;
projects / mesa.git / blobdiff