return 1;
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_FP16:
+ case PIPE_SHADER_CAP_FP16_DERIVATIVES:
+ case PIPE_SHADER_CAP_INT16:
return 0;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
}
}
-static unsigned
-get_max_threads(const struct gen_device_info *devinfo)
-{
- /* Limit max_threads to 64 for the GPGPU_WALKER command. */
- return MIN2(64, devinfo->max_cs_threads);
-}
-
-uint32_t
-iris_get_max_var_invocations(const struct iris_screen *screen)
-{
- const unsigned max_threads = get_max_threads(&screen->devinfo);
-
- /* Constants used for ARB_compute_variable_group_size. The compiler will
- * use the maximum to decide which SIMDs can be used. If we top this like
- * max_invocations, that would prevent SIMD8 / SIMD16 to be considered.
- *
- * TODO: To avoid the trade off above between having the lower maximum
- * vs. always using SIMD32, keep all three shader variants (for each SIMD)
- * and select a suitable one at dispatch time.
- */
- const uint32_t max_var_invocations =
- (max_threads >= 64 ? 8 : (max_threads >= 32 ? 16 : 32)) * max_threads;
- assert(max_var_invocations >= 512);
- return max_var_invocations;
-}
-
static int
iris_get_compute_param(struct pipe_screen *pscreen,
enum pipe_shader_ir ir_type,
void *ret)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
+ const struct gen_device_info *devinfo = &screen->devinfo;
- const unsigned max_threads = get_max_threads(&screen->devinfo);
+ /* Limit max_threads to 64 for the GPGPU_WALKER command. */
+ const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
const uint32_t max_invocations = 32 * max_threads;
#define RET(x) do { \
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
/* MaxComputeWorkGroupInvocations */
+ case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+ /* MaxComputeVariableGroupInvocations */
RET((uint64_t []) { max_invocations });
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
RET((uint32_t []) { BRW_SUBGROUP_SIZE });
- case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
- /* MaxComputeVariableGroupInvocations */
- RET((uint64_t []) { iris_get_max_var_invocations(screen) });
-
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
}
+static bool
+iris_init_identifier_bo(struct iris_screen *screen)
+{
+ void *bo_map;
+
+ bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
+ if (!bo_map)
+ return false;
+
+ screen->workaround_bo->kflags |= EXEC_OBJECT_CAPTURE;
+ screen->workaround_address = (struct iris_address) {
+ .bo = screen->workaround_bo,
+ .offset = ALIGN(
+ intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8),
+ };
+
+ iris_bo_unmap(screen->workaround_bo);
+
+ return true;
+}
+
struct pipe_screen *
iris_screen_create(int fd, const struct pipe_screen_config *config)
{
if (!screen->workaround_bo)
return NULL;
- screen->workaround_address = (struct iris_address) {
- .bo = screen->workaround_bo,
- .offset = 0,
- };
+ if (!iris_init_identifier_bo(screen))
+ return NULL;
brw_process_intel_debug_variable();