#include "util/debug.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
+#include "util/u_transfer_helper.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
+#include "util/xmlconfig.h"
#include "drm-uapi/i915_drm.h"
#include "iris_context.h"
#include "iris_defines.h"
static const char *
iris_get_vendor(struct pipe_screen *pscreen)
{
- return "Mesa Project";
+ return "Intel";
}
static const char *
iris_get_name(struct pipe_screen *pscreen)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
+ static char buf[128];
const char *chipset;
switch (screen->pci_id) {
chipset = "Unknown Intel Chipset";
break;
}
- return &chipset[9];
+
+ snprintf(buf, sizeof(buf), "Mesa %s", chipset);
+ return buf;
+}
+
+static uint64_t
+get_aperture_size(int fd)
+{
+ struct drm_i915_gem_get_aperture aperture = {};
+ drm_ioctl(fd, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
+ return aperture.aper_size;
}
static int
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
- case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+ case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
case PIPE_CAP_DRAW_INDIRECT:
+ case PIPE_CAP_MULTI_DRAW_INDIRECT:
+ case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
+ case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
case PIPE_CAP_ACCELERATED:
case PIPE_CAP_UMA:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
case PIPE_CAP_DOUBLES:
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
- case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
case PIPE_CAP_TGSI_TXQS:
- case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_TGSI_BALLOT:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
- case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_NIR_COMPACT_ARRAYS:
+ case PIPE_CAP_DRAW_PARAMETERS:
+ case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
+ case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
+ case PIPE_CAP_INVALIDATE_BUFFER:
+ case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
return true;
-
+ case PIPE_CAP_FBFETCH:
+ /* TODO: Support non-coherent FB fetch on Broadwell */
+ return devinfo->gen >= 9 ? BRW_MAX_DRAW_BUFFERS : 0;
+ case PIPE_CAP_FBFETCH_COHERENT:
+ case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
+ case PIPE_CAP_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_SHADER_STENCIL_EXPORT:
+ case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
+ case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
+ return devinfo->gen >= 9;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
return BRW_MAX_DRAW_BUFFERS;
- case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
+ return 16384;
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
- return 15; /* 16384x16384 */
+ return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 12; /* 2048x2048 */
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
/* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
return 32;
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return IRIS_MAP_BUFFER_ALIGNMENT;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
/* Choose a cacheline (64 bytes) so that we can safely have the CPU and
* GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
return 0x8086;
case PIPE_CAP_DEVICE_ID:
return screen->pci_id;
- case PIPE_CAP_VIDEO_MEMORY:
- return 0xffffffff; // XXX: bogus
+ case PIPE_CAP_VIDEO_MEMORY: {
+ /* Once a batch uses more than 75% of the maximum mappable size, we
+ * assume that there's some fragmentation, and we start doing extra
+ * flushing, etc. That's the big cliff apps will care about.
+ */
+ const unsigned gpu_mappable_megabytes =
+ (screen->aperture_bytes * 3 / 4) / (1024 * 1024);
+
+ const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
+ const long system_page_size = sysconf(_SC_PAGE_SIZE);
+
+ if (system_memory_pages <= 0 || system_page_size <= 0)
+ return -1;
+
+ const uint64_t system_memory_bytes =
+ (uint64_t) system_memory_pages * (uint64_t) system_page_size;
+
+ const unsigned system_memory_megabytes =
+ (unsigned) (system_memory_bytes / (1024 * 1024));
+
+ return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
+ }
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
/* AMD_pinned_memory assumes the flexibility of using client memory
*/
return devinfo->has_llc;
+ case PIPE_CAP_CONTEXT_PRIORITY_MASK:
+ return PIPE_CONTEXT_PRIORITY_LOW |
+ PIPE_CONTEXT_PRIORITY_MEDIUM |
+ PIPE_CONTEXT_PRIORITY_HIGH;
+
// XXX: don't hardcode 00:00:02.0 PCI here
case PIPE_CAP_PCI_GROUP:
return 0;
enum pipe_shader_type p_stage,
enum pipe_shader_cap param)
{
- struct iris_screen *screen = (struct iris_screen *)pscreen;
- struct brw_compiler *compiler = screen->compiler;
gl_shader_stage stage = stage_from_pipe(p_stage);
/* this is probably not totally correct.. but it's a start: */
return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
+ case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+ return 1;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
- case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
- case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
void *ret)
{
struct iris_screen *screen = (struct iris_screen *)pscreen;
- struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
- // XXX: cherryview fusing
-
const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
const uint32_t max_invocations = 32 * max_threads;
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
iris_bo_unreference(screen->workaround_bo);
+ u_transfer_helper_destroy(pscreen->transfer_helper);
+ iris_bufmgr_destroy(screen->bufmgr);
+ disk_cache_destroy(screen->disk_cache);
ralloc_free(screen);
}
return screen->compiler->glsl_compiler_options[stage].NirOptions;
}
+static struct disk_cache *
+iris_get_disk_shader_cache(struct pipe_screen *pscreen)
+{
+ struct iris_screen *screen = (struct iris_screen *) pscreen;
+ return screen->disk_cache;
+}
+
static int
iris_getparam(struct iris_screen *screen, int param, int *value)
{
return 0;
}
-static bool
-iris_getparam_boolean(struct iris_screen *screen, int param)
-{
- int value = 0;
- return (iris_getparam(screen, param, &value) == 0) && value;
-}
-
static int
iris_getparam_integer(struct iris_screen *screen, int param)
{
struct pipe_debug_callback *dbg = data;
unsigned id = 0;
va_list args;
+ va_start(args, fmt);
- if (!dbg->debug_message)
- return;
+ if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
+ va_list args_copy;
+ va_copy(args_copy, args);
+ vfprintf(stderr, fmt, args_copy);
+ va_end(args_copy);
+ }
+
+ if (dbg->debug_message) {
+ dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
+ }
- va_start(args, fmt);
- dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
va_end(args);
}
struct pipe_screen *
-iris_screen_create(int fd)
+iris_screen_create(int fd, const struct pipe_screen_config *config)
{
struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
if (!screen)
if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
return NULL;
+ if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
+ return NULL;
+
screen->devinfo.timestamp_frequency =
iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
+ screen->aperture_bytes = get_aperture_size(fd);
+
+ if (getenv("INTEL_NO_HW") != NULL)
+ screen->no_hw = true;
+
screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
if (!screen->bufmgr)
return NULL;
brw_process_intel_debug_variable();
+ screen->driconf.dual_color_blend_by_location =
+ driQueryOptionb(config->options, "dual_color_blend_by_location");
+
screen->precompile = env_var_as_boolean("shader_precompile", true);
- bool hw_has_swizzling = false; // XXX: detect?
- isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
+ isl_device_init(&screen->isl_dev, &screen->devinfo, false);
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
screen->compiler->shader_debug_log = iris_shader_debug_log;
screen->compiler->shader_perf_log = iris_shader_perf_log;
screen->compiler->supports_pull_constants = false;
+ screen->compiler->supports_shader_constants = true;
+
+ iris_disk_cache_init(screen);
slab_create_parent(&screen->transfer_pool,
sizeof(struct iris_transfer), 64);
pscreen->get_compute_param = iris_get_compute_param;
pscreen->get_paramf = iris_get_paramf;
pscreen->get_compiler_options = iris_get_compiler_options;
+ pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
pscreen->is_format_supported = iris_is_format_supported;
pscreen->context_create = iris_create_context;
pscreen->flush_frontbuffer = iris_flush_frontbuffer;
projects / mesa.git / blobdiff