#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "pipe/p_screen.h"
+#include "util/debug.h"
#include "util/u_inlines.h"
#include "util/u_format.h"
+#include "util/u_transfer_helper.h"
#include "util/u_upload_mgr.h"
#include "util/ralloc.h"
#include "drm-uapi/i915_drm.h"
#include "iris_context.h"
#include "iris_defines.h"
+#include "iris_fence.h"
#include "iris_pipe.h"
#include "iris_resource.h"
#include "iris_screen.h"
chipset = "Unknown Intel Chipset";
break;
}
- return &chipset[9];
+ return chipset;
}
static int
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
- case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
+ case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
- case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_QUERY_SO_OVERFLOW:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
+ case PIPE_CAP_TGSI_TXQS:
case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_TGSI_BALLOT:
case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
case PIPE_CAP_TEXTURE_GATHER_SM5:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+ case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_NIR_COMPACT_ARRAYS:
return true;
-
+ case PIPE_CAP_TGSI_FS_FBFETCH:
+ case PIPE_CAP_POST_DEPTH_COVERAGE:
+ case PIPE_CAP_SHADER_STENCIL_EXPORT:
+ return devinfo->gen >= 9;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_MAX_RENDER_TARGETS:
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return true; // XXX: ?????
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return 1 << 27; /* 128MB */
+ return IRIS_MAX_TEXTURE_BUFFER_SIZE;
case PIPE_CAP_MAX_VIEWPORTS:
return 16;
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
case PIPE_CAP_DEVICE_ID:
return screen->pci_id;
case PIPE_CAP_VIDEO_MEMORY:
- return 0xffffffff; // XXX: bogus
+ return INT_MAX; // XXX: bogus
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
/* AMD_pinned_memory assumes the flexibility of using client memory
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 0;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
- return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
- return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
- return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
- return 1;
+ /* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
+ * which we don't want. Our compiler backend will check brw_compiler's
+ * options and call nir_lower_indirect_derefs appropriately anyway.
+ */
+ return true;
case PIPE_SHADER_CAP_SUBROUTINES:
return 0;
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- return 0;
+ return 1 << PIPE_SHADER_IR_NIR;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
enum pipe_compute_cap param,
void *ret)
{
- /* TODO: compute shaders */
- return 0;
+ struct iris_screen *screen = (struct iris_screen *)pscreen;
+ struct brw_compiler *compiler = screen->compiler;
+ const struct gen_device_info *devinfo = &screen->devinfo;
+
+ const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
+ const uint32_t max_invocations = 32 * max_threads;
+
+#define RET(x) do { \
+ if (ret) \
+ memcpy(ret, x, sizeof(x)); \
+ return sizeof(x); \
+} while (0)
+
+ switch (param) {
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ RET((uint32_t []){ 32 });
+
+ case PIPE_COMPUTE_CAP_IR_TARGET:
+ if (ret)
+ strcpy(ret, "gen");
+ return 4;
+
+ case PIPE_COMPUTE_CAP_GRID_DIMENSION:
+ RET((uint64_t []) { 3 });
+
+ case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
+ RET(((uint64_t []) { 65535, 65535, 65535 }));
+
+ case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
+ /* MaxComputeWorkGroupSize[0..2] */
+ RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
+
+ case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
+ /* MaxComputeWorkGroupInvocations */
+ RET((uint64_t []) { max_invocations });
+
+ case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
+ /* MaxComputeSharedMemorySize */
+ RET((uint64_t []) { 64 * 1024 });
+
+ case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
+ RET((uint32_t []) { 1 });
+
+ case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
+ RET((uint32_t []) { BRW_SUBGROUP_SIZE });
+
+ case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
+ case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
+ case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
+ case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
+ case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
+ case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
+ case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+ // XXX: I think these are for Clover...
+ return 0;
+
+ default:
+ unreachable("unknown compute param");
+ }
}
static uint64_t
{
struct iris_screen *screen = (struct iris_screen *) pscreen;
iris_bo_unreference(screen->workaround_bo);
+ u_transfer_helper_destroy(pscreen->transfer_helper);
+ iris_bufmgr_destroy(screen->bufmgr);
ralloc_free(screen);
}
-static void
-iris_fence_reference(struct pipe_screen *screen,
- struct pipe_fence_handle **ptr,
- struct pipe_fence_handle *fence)
-{
-}
-
-static boolean
-iris_fence_finish(struct pipe_screen *screen,
- struct pipe_context *ctx,
- struct pipe_fence_handle *fence,
- uint64_t timeout)
-{
- return true;
-}
-
static void
iris_query_memory_info(struct pipe_screen *pscreen,
struct pipe_memory_info *info)
if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
return NULL;
+ if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
+ return NULL;
+
screen->devinfo.timestamp_frequency =
iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
brw_process_intel_debug_variable();
- bool hw_has_swizzling = false; // XXX: detect?
- isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
+ screen->precompile = env_var_as_boolean("shader_precompile", true);
+
+ isl_device_init(&screen->isl_dev, &screen->devinfo, false);
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
screen->compiler->shader_debug_log = iris_shader_debug_log;
screen->compiler->shader_perf_log = iris_shader_perf_log;
+ screen->compiler->supports_pull_constants = false;
slab_create_parent(&screen->transfer_pool,
sizeof(struct iris_transfer), 64);
+ screen->subslice_total =
+ iris_getparam_integer(screen, I915_PARAM_SUBSLICE_TOTAL);
+ assert(screen->subslice_total >= 1);
+
struct pipe_screen *pscreen = &screen->base;
+ iris_init_screen_fence_functions(pscreen);
iris_init_screen_resource_functions(pscreen);
pscreen->destroy = iris_destroy_screen;
pscreen->context_create = iris_create_context;
pscreen->flush_frontbuffer = iris_flush_frontbuffer;
pscreen->get_timestamp = iris_get_timestamp;
- pscreen->fence_reference = iris_fence_reference;
- pscreen->fence_finish = iris_fence_finish;
pscreen->query_memory_info = iris_query_memory_info;
return pscreen;
projects / mesa.git / blobdiff