chipset = "Unknown Intel Chipset";
break;
}
- return &chipset[9];
+ return chipset;
}
static int
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
case PIPE_CAP_LOAD_CONSTBUF:
+ case PIPE_CAP_NIR_COMPACT_ARRAYS:
return true;
case PIPE_CAP_TGSI_FS_FBFETCH:
case PIPE_CAP_POST_DEPTH_COVERAGE:
case PIPE_CAP_DEVICE_ID:
return screen->pci_id;
case PIPE_CAP_VIDEO_MEMORY:
- return 0xffffffff; // XXX: bogus
+ return INT_MAX; // XXX: bogus
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
+ case PIPE_CAP_MAX_VARYINGS:
return 32;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
/* AMD_pinned_memory assumes the flexibility of using client memory
struct brw_compiler *compiler = screen->compiler;
const struct gen_device_info *devinfo = &screen->devinfo;
- // XXX: cherryview fusing
-
const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
const uint32_t max_invocations = 32 * max_threads;
if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
return NULL;
+ if (screen->devinfo.gen < 8 || screen->devinfo.is_cherryview)
+ return NULL;
+
screen->devinfo.timestamp_frequency =
iris_getparam_integer(screen, I915_PARAM_CS_TIMESTAMP_FREQUENCY);
screen->precompile = env_var_as_boolean("shader_precompile", true);
- bool hw_has_swizzling = false; // XXX: detect?
- isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
+ isl_device_init(&screen->isl_dev, &screen->devinfo, false);
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
screen->compiler->shader_debug_log = iris_shader_debug_log;