#include "util/u_transfer.h"
#include "util/u_upload_mgr.h"
#include "util/u_viewport.h"
+#include "util/u_memory.h"
#include "drm-uapi/i915_drm.h"
#include "nir.h"
#include "intel/compiler/brw_compiler.h"
#include "iris_genx_macros.h"
#include "intel/common/gen_guardband.h"
-static uint32_t
-mocs(const struct iris_bo *bo, const struct isl_device *dev)
-{
- return bo && bo->external ? dev->mocs.external : dev->mocs.internal;
-}
-
/**
* Statically assert that PIPE_* enums match the hardware packets.
* (As long as they match, we don't need to translate them.)
struct iris_bo *bo = iris_resource_bo(*out_res);
iris_use_pinned_bo(batch, bo, false);
- *out_offset += iris_bo_offset_from_base_address(bo);
+ iris_record_state_size(batch->state_sizes,
+ bo->gtt_offset + *out_offset, size);
- iris_record_state_size(batch->state_sizes, *out_offset, size);
+ *out_offset += iris_bo_offset_from_base_address(bo);
return ptr;
}
static void
flush_before_state_base_change(struct iris_batch *batch)
{
+ const struct gen_device_info *devinfo = &batch->screen->devinfo;
+
/* Flush before emitting STATE_BASE_ADDRESS.
*
* This isn't documented anywhere in the PRM. However, it seems to be
"change STATE_BASE_ADDRESS (flushes)",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- PIPE_CONTROL_DATA_CACHE_FLUSH);
+ PIPE_CONTROL_DATA_CACHE_FLUSH |
+ /* GEN:BUG:1606662791:
+ *
+ * Software must program PIPE_CONTROL command
+ * with "HDC Pipeline Flush" prior to
+ * programming of the below two non-pipeline
+ * state :
+ * * STATE_BASE_ADDRESS
+ * * 3DSTATE_BINDING_TABLE_POOL_ALLOC
+ */
+ ((GEN_GEN == 12 && devinfo->revision == 0 /* A0 */ ?
+ PIPE_CONTROL_FLUSH_HDC : 0)));
}
static void
}
static void
-iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
- bool has_slm, bool wants_dc_cache)
+iris_emit_l3_config(struct iris_batch *batch,
+ const struct gen_l3_config *cfg)
{
uint32_t reg_val;
#endif
iris_pack_state(L3_ALLOCATION_REG, ®_val, reg) {
-#if GEN_GEN < 12
- reg.SLMEnable = has_slm;
+#if GEN_GEN < 11
+ reg.SLMEnable = cfg->n[GEN_L3P_SLM] > 0;
#endif
#if GEN_GEN == 11
/* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
_iris_emit_lri(batch, L3_ALLOCATION_REG_num, reg_val);
}
-static void
-iris_emit_default_l3_config(struct iris_batch *batch,
- const struct gen_device_info *devinfo,
- bool compute)
-{
- bool wants_dc_cache = true;
- bool has_slm = compute;
- const struct gen_l3_weights w =
- gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
- const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
- iris_emit_l3_config(batch, cfg, has_slm, wants_dc_cache);
-}
-
-#if GEN_GEN == 9 || GEN_GEN == 10
+#if GEN_GEN == 9
static void
iris_enable_obj_preemption(struct iris_batch *batch, bool enable)
{
}
}
+#if GEN_GEN >= 12
+static void
+init_aux_map_state(struct iris_batch *batch);
+#endif
+
/**
* Upload the initial GPU state for a render context.
*
emit_pipeline_select(batch, _3D);
- iris_emit_default_l3_config(batch, devinfo, false);
+ iris_emit_l3_config(batch, batch->screen->l3_config_3d);
init_state_base_address(batch);
#endif
#if GEN_GEN == 11
- iris_pack_state(GENX(SAMPLER_MODE), ®_val, reg) {
- reg.HeaderlessMessageforPreemptableContexts = 1;
- reg.HeaderlessMessageforPreemptableContextsMask = 1;
- }
- iris_emit_lri(batch, SAMPLER_MODE, reg_val);
+ iris_pack_state(GENX(TCCNTLREG), ®_val, reg) {
+ reg.L3DataPartialWriteMergingEnable = true;
+ reg.ColorZPartialWriteMergingEnable = true;
+ reg.URBPartialWriteMergingEnable = true;
+ reg.TCDisable = true;
+ }
+ iris_emit_lri(batch, TCCNTLREG, reg_val);
- /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
- iris_pack_state(GENX(HALF_SLICE_CHICKEN7), ®_val, reg) {
- reg.EnabledTexelOffsetPrecisionFix = 1;
- reg.EnabledTexelOffsetPrecisionFixMask = 1;
- }
- iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
+ iris_pack_state(GENX(SAMPLER_MODE), ®_val, reg) {
+ reg.HeaderlessMessageforPreemptableContexts = 1;
+ reg.HeaderlessMessageforPreemptableContextsMask = 1;
+ }
+ iris_emit_lri(batch, SAMPLER_MODE, reg_val);
- /* Hardware specification recommends disabling repacking for the
- * compatibility with decompression mechanism in display controller.
- */
- if (devinfo->disable_ccs_repack) {
- iris_pack_state(GENX(CACHE_MODE_0), ®_val, reg) {
- reg.DisableRepackingforCompression = true;
- reg.DisableRepackingforCompressionMask = true;
- }
- iris_emit_lri(batch, CACHE_MODE_0, reg_val);
+ /* Bit 1 must be set in HALF_SLICE_CHICKEN7. */
+ iris_pack_state(GENX(HALF_SLICE_CHICKEN7), ®_val, reg) {
+ reg.EnabledTexelOffsetPrecisionFix = 1;
+ reg.EnabledTexelOffsetPrecisionFixMask = 1;
+ }
+ iris_emit_lri(batch, HALF_SLICE_CHICKEN7, reg_val);
+
+ /* Hardware specification recommends disabling repacking for the
+ * compatibility with decompression mechanism in display controller.
+ */
+ if (devinfo->disable_ccs_repack) {
+ iris_pack_state(GENX(CACHE_MODE_0), ®_val, reg) {
+ reg.DisableRepackingforCompression = true;
+ reg.DisableRepackingforCompressionMask = true;
}
+ iris_emit_lri(batch, CACHE_MODE_0, reg_val);
+ }
- iris_upload_slice_hashing_state(batch);
+ iris_upload_slice_hashing_state(batch);
#endif
/* 3DSTATE_DRAWING_RECTANGLE is non-pipelined, so we want to avoid
iris_alloc_push_constants(batch);
-#if GEN_GEN == 10
- /* Gen11+ is enabled for us by the kernel. */
- iris_enable_obj_preemption(batch, true);
+#if GEN_GEN >= 12
+ init_aux_map_state(batch);
#endif
}
{
UNUSED const struct gen_device_info *devinfo = &batch->screen->devinfo;
+ /* GEN:BUG:1607854226:
+ *
+ * Start with pipeline in 3D mode to set the STATE_BASE_ADDRESS.
+ */
+#if GEN_GEN == 12
+ emit_pipeline_select(batch, _3D);
+#else
emit_pipeline_select(batch, GPGPU);
+#endif
- iris_emit_default_l3_config(batch, devinfo, true);
+ iris_emit_l3_config(batch, batch->screen->l3_config_cs);
init_state_base_address(batch);
+#if GEN_GEN == 12
+ emit_pipeline_select(batch, GPGPU);
+#endif
+
#if GEN_GEN == 9
if (devinfo->is_geminilake)
init_glk_barrier_mode(batch, GLK_BARRIER_MODE_GPGPU);
#endif
+
+#if GEN_GEN >= 12
+ init_aux_map_state(batch);
+#endif
+
}
struct iris_vertex_buffer_state {
uint32_t packets[GENX(3DSTATE_DEPTH_BUFFER_length) +
GENX(3DSTATE_STENCIL_BUFFER_length) +
GENX(3DSTATE_HIER_DEPTH_BUFFER_length) +
- GENX(3DSTATE_CLEAR_PARAMS_length)];
+ GENX(3DSTATE_CLEAR_PARAMS_length) +
+ GENX(MI_LOAD_REGISTER_IMM_length) * 2];
};
/**
state->stencil[0].writemask != 0 ||
(two_sided_stencil && state->stencil[1].writemask != 0);
- /* The state tracker needs to optimize away EQUAL writes for us. */
+ /* gallium frontends need to optimize away EQUAL writes for us. */
assert(!(state->depth.func == PIPE_FUNC_EQUAL && state->depth.writemask));
iris_pack_command(GENX(3DSTATE_WM_DEPTH_STENCIL), cso->wmds, wmds) {
struct iris_shader_state *shs = &ice->state.shaders[stage];
const struct shader_info *info = iris_get_shader_info(ice, stage);
- /* We assume the state tracker will call pipe->bind_sampler_states()
+ /* We assume gallium frontends will call pipe->bind_sampler_states()
* if the program's number of textures changes.
*/
unsigned count = info ? util_last_bit(info->textures_used) : 0;
return;
struct pipe_resource *res = shs->sampler_table.res;
- shs->sampler_table.offset +=
- iris_bo_offset_from_base_address(iris_resource_bo(res));
+ struct iris_bo *bo = iris_resource_bo(res);
- iris_record_state_size(ice->state.sizes, shs->sampler_table.offset, size);
+ iris_record_state_size(ice->state.sizes,
+ bo->gtt_offset + shs->sampler_table.offset, size);
+
+ shs->sampler_table.offset += iris_bo_offset_from_base_address(bo);
/* Make sure all land in the same BO */
iris_border_color_pool_reserve(ice, IRIS_MAX_TEXTURE_SAMPLERS);
.format = format,
.swizzle = swizzle,
.stride_B = cpp,
- .mocs = mocs(res->bo, isl_dev));
+ .mocs = iris_mocs(res->bo, isl_dev));
}
#define SURFACE_STATE_ALIGNMENT 64
/**
* Allocate several contiguous SURFACE_STATE structures, one for each
- * supported auxiliary surface mode.
+ * supported auxiliary surface mode. This only allocates the CPU-side
+ * copy, they will need to be uploaded later after they're filled in.
*/
-static void *
-alloc_surface_states(struct u_upload_mgr *mgr,
- struct iris_state_ref *ref,
+static void
+alloc_surface_states(struct iris_surface_state *surf_state,
unsigned aux_usages)
{
const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length);
assert(aux_usages != 0);
+ /* In case we're re-allocating them... */
+ free(surf_state->cpu);
+
+ surf_state->num_states = util_bitcount(aux_usages);
+ surf_state->cpu = calloc(surf_state->num_states, surf_size);
+ surf_state->ref.offset = 0;
+ pipe_resource_reference(&surf_state->ref.res, NULL);
+
+ assert(surf_state->cpu);
+}
+
+/**
+ * Upload the CPU side SURFACE_STATEs into a GPU buffer.
+ */
+static void
+upload_surface_states(struct u_upload_mgr *mgr,
+ struct iris_surface_state *surf_state)
+{
+ const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length);
+ const unsigned bytes = surf_state->num_states * surf_size;
+
void *map =
- upload_state(mgr, ref, util_bitcount(aux_usages) * surf_size,
- SURFACE_STATE_ALIGNMENT);
+ upload_state(mgr, &surf_state->ref, bytes, SURFACE_STATE_ALIGNMENT);
- ref->offset += iris_bo_offset_from_base_address(iris_resource_bo(ref->res));
+ surf_state->ref.offset +=
+ iris_bo_offset_from_base_address(iris_resource_bo(surf_state->ref.res));
- return map;
+ if (map)
+ memcpy(map, surf_state->cpu, bytes);
+}
+
+/**
+ * Update resource addresses in a set of SURFACE_STATE descriptors,
+ * and re-upload them if necessary.
+ */
+static bool
+update_surface_state_addrs(struct u_upload_mgr *mgr,
+ struct iris_surface_state *surf_state,
+ struct iris_bo *bo)
+{
+ if (surf_state->bo_address == bo->gtt_offset)
+ return false;
+
+ STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) % 64 == 0);
+ STATIC_ASSERT(GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_bits) == 64);
+
+ uint64_t *ss_addr = (uint64_t *) &surf_state->cpu[GENX(RENDER_SURFACE_STATE_SurfaceBaseAddress_start) / 32];
+
+ /* First, update the CPU copies. We assume no other fields exist in
+ * the QWord containing Surface Base Address.
+ */
+ for (unsigned i = 0; i < surf_state->num_states; i++) {
+ *ss_addr = *ss_addr - surf_state->bo_address + bo->gtt_offset;
+ ss_addr = ((void *) ss_addr) + SURFACE_STATE_ALIGNMENT;
+ }
+
+ /* Next, upload the updated copies to a GPU buffer. */
+ upload_surface_states(mgr, surf_state);
+
+ surf_state->bo_address = bo->gtt_offset;
+
+ return true;
}
#if GEN_GEN == 8
struct iris_resource *res,
enum pipe_texture_target target,
struct isl_view *view,
+ uint32_t *offset_to_tile,
uint32_t *tile_x_sa,
uint32_t *tile_y_sa,
struct isl_surf *surf)
{
-
*surf = res->surf;
const enum isl_dim_layout dim_layout =
assert(view->levels == 1 && view->array_len == 1);
assert(*tile_x_sa == 0 && *tile_y_sa == 0);
- res->offset += iris_resource_get_tile_offsets(res, view->base_level,
- view->base_array_layer,
- tile_x_sa, tile_y_sa);
+ *offset_to_tile = iris_resource_get_tile_offsets(res, view->base_level,
+ view->base_array_layer,
+ tile_x_sa, tile_y_sa);
const unsigned l = view->base_level;
surf->logical_level0_px.width = minify(surf->logical_level0_px.width, l);
struct isl_surf *surf,
struct isl_view *view,
unsigned aux_usage,
+ uint32_t extra_main_offset,
uint32_t tile_x_sa,
uint32_t tile_y_sa)
{
struct isl_surf_fill_state_info f = {
.surf = surf,
.view = view,
- .mocs = mocs(res->bo, isl_dev),
- .address = res->bo->gtt_offset + res->offset,
+ .mocs = iris_mocs(res->bo, isl_dev),
+ .address = res->bo->gtt_offset + res->offset + extra_main_offset,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
};
isv->res = (struct iris_resource *) tex;
- void *map = alloc_surface_states(ice->state.surface_uploader,
- &isv->surface_state,
- isv->res->aux.sampler_usages);
- if (!unlikely(map))
- return NULL;
+ alloc_surface_states(&isv->surface_state, isv->res->aux.sampler_usages);
+
+ isv->surface_state.bo_address = isv->res->bo->gtt_offset;
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_TEXTURE_BIT;
.usage = usage,
};
+ void *map = isv->surface_state.cpu;
+
/* Fill out SURFACE_STATE for this view. */
if (tmpl->target != PIPE_BUFFER) {
isv->view.base_level = tmpl->u.tex.first_level;
* surface state with HiZ.
*/
fill_surface_state(&screen->isl_dev, map, isv->res, &isv->res->surf,
- &isv->view, aux_usage, 0, 0);
+ &isv->view, aux_usage, 0, 0, 0);
map += SURFACE_STATE_ALIGNMENT;
}
tmpl->u.buf.offset, tmpl->u.buf.size);
}
+ upload_surface_states(ice->state.surface_uploader, &isv->surface_state);
+
return &isv->base;
}
{
struct iris_sampler_view *isv = (void *) state;
pipe_resource_reference(&state->texture, NULL);
- pipe_resource_reference(&isv->surface_state.res, NULL);
+ pipe_resource_reference(&isv->surface_state.ref.res, NULL);
+ free(isv->surface_state.cpu);
free(isv);
}
return psurf;
- void *map = alloc_surface_states(ice->state.surface_uploader,
- &surf->surface_state,
- res->aux.possible_usages);
- if (!unlikely(map)) {
- pipe_resource_reference(&surf->surface_state.res, NULL);
- return NULL;
- }
+ alloc_surface_states(&surf->surface_state, res->aux.possible_usages);
+ surf->surface_state.bo_address = res->bo->gtt_offset;
#if GEN_GEN == 8
- void *map_read = alloc_surface_states(ice->state.surface_uploader,
- &surf->surface_state_read,
- res->aux.possible_usages);
- if (!unlikely(map_read)) {
- pipe_resource_reference(&surf->surface_state_read.res, NULL);
- return NULL;
- }
+ alloc_surface_states(&surf->surface_state_read, res->aux.possible_usages);
+ surf->surface_state_read.bo_address = res->bo->gtt_offset;
#endif
if (!isl_format_is_compressed(res->surf.format)) {
if (iris_resource_unfinished_aux_import(res))
iris_resource_finish_aux_import(&screen->base, res);
+ void *map = surf->surface_state.cpu;
+ UNUSED void *map_read = surf->surface_state_read.cpu;
+
/* This is a normal surface. Fill out a SURFACE_STATE for each possible
* auxiliary surface mode and return the pipe_surface.
*/
unsigned aux_modes = res->aux.possible_usages;
while (aux_modes) {
-#if GEN_GEN == 8
- uint32_t offset = res->offset;
-#endif
enum isl_aux_usage aux_usage = u_bit_scan(&aux_modes);
fill_surface_state(&screen->isl_dev, map, res, &res->surf,
- view, aux_usage, 0, 0);
+ view, aux_usage, 0, 0, 0);
map += SURFACE_STATE_ALIGNMENT;
#if GEN_GEN == 8
struct isl_surf surf;
- uint32_t tile_x_sa = 0, tile_y_sa = 0;
+ uint32_t offset_to_tile = 0, tile_x_sa = 0, tile_y_sa = 0;
get_rt_read_isl_surf(devinfo, res, target, read_view,
- &tile_x_sa, &tile_y_sa, &surf);
+ &offset_to_tile, &tile_x_sa, &tile_y_sa, &surf);
fill_surface_state(&screen->isl_dev, map_read, res, &surf, read_view,
- aux_usage, tile_x_sa, tile_y_sa);
- /* Restore offset because we change offset in case of handling
- * non_coherent fb fetch
- */
- res->offset = offset;
+ aux_usage, offset_to_tile, tile_x_sa, tile_y_sa);
map_read += SURFACE_STATE_ALIGNMENT;
#endif
}
+ upload_surface_states(ice->state.surface_uploader, &surf->surface_state);
+
+#if GEN_GEN == 8
+ upload_surface_states(ice->state.surface_uploader,
+ &surf->surface_state_read);
+#endif
+
return psurf;
}
* texture, the tile offsets may be anything and we can't rely on
* X/Y Offset.
*
- * Return NULL to force the state tracker to take fallback paths.
+ * Return NULL to force gallium frontends to take fallback paths.
*/
if (view->array_len > 1 || GEN_GEN == 8)
return NULL;
struct isl_surf_fill_state_info f = {
.surf = &isl_surf,
.view = view,
- .mocs = mocs(res->bo, &screen->isl_dev),
+ .mocs = iris_mocs(res->bo, &screen->isl_dev),
.address = res->bo->gtt_offset + offset_B,
.x_offset_sa = tile_x_sa,
.y_offset_sa = tile_y_sa,
};
- isl_surf_fill_state_s(&screen->isl_dev, map, &f);
+ isl_surf_fill_state_s(&screen->isl_dev, surf->surface_state.cpu, &f);
+
+ upload_surface_states(ice->state.surface_uploader, &surf->surface_state);
+
return psurf;
}
{
struct iris_context *ice = (struct iris_context *) ctx;
struct iris_screen *screen = (struct iris_screen *)ctx->screen;
- const struct gen_device_info *devinfo = &screen->devinfo;
gl_shader_stage stage = stage_from_pipe(p_stage);
struct iris_shader_state *shs = &ice->state.shaders[stage];
#if GEN_GEN == 8
const struct pipe_image_view *img = &p_images[i];
struct iris_resource *res = (void *) img->resource;
- void *map =
- alloc_surface_states(ice->state.surface_uploader,
- &iv->surface_state, 1 << ISL_AUX_USAGE_NONE);
- if (!unlikely(map))
- return;
-
util_copy_image_view(&iv->base, img);
shs->bound_image_views |= 1 << (start_slot + i);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
res->bind_stages |= 1 << stage;
- isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
- enum isl_format isl_fmt =
- iris_format_for_usage(devinfo, img->format, usage).fmt;
+ enum isl_format isl_fmt = iris_image_view_get_format(ice, img);
- bool untyped_fallback = false;
+ /* Render compression with images supported on gen12+ only. */
+ unsigned aux_usages = GEN_GEN >= 12 ? res->aux.possible_usages :
+ 1 << ISL_AUX_USAGE_NONE;
- if (img->shader_access & PIPE_IMAGE_ACCESS_READ) {
- /* On Gen8, try to use typed surfaces reads (which support a
- * limited number of formats), and if not possible, fall back
- * to untyped reads.
- */
- untyped_fallback = GEN_GEN == 8 &&
- !isl_has_matching_typed_storage_image_format(devinfo, isl_fmt);
+ alloc_surface_states(&iv->surface_state, aux_usages);
+ iv->surface_state.bo_address = res->bo->gtt_offset;
- if (untyped_fallback)
- isl_fmt = ISL_FORMAT_RAW;
- else
- isl_fmt = isl_lower_storage_image_format(devinfo, isl_fmt);
- }
+ void *map = iv->surface_state.cpu;
if (res->base.target != PIPE_BUFFER) {
struct isl_view view = {
.base_array_layer = img->u.tex.first_layer,
.array_len = img->u.tex.last_layer - img->u.tex.first_layer + 1,
.swizzle = ISL_SWIZZLE_IDENTITY,
- .usage = usage,
+ .usage = ISL_SURF_USAGE_STORAGE_BIT,
};
- if (untyped_fallback) {
+ /* If using untyped fallback. */
+ if (isl_fmt == ISL_FORMAT_RAW) {
fill_buffer_surface_state(&screen->isl_dev, res, map,
isl_fmt, ISL_SWIZZLE_IDENTITY,
0, res->bo->size);
} else {
- /* Images don't support compression */
- unsigned aux_modes = 1 << ISL_AUX_USAGE_NONE;
+ unsigned aux_modes = aux_usages;
while (aux_modes) {
enum isl_aux_usage usage = u_bit_scan(&aux_modes);
fill_surface_state(&screen->isl_dev, map, res, &res->surf,
- &view, usage, 0, 0);
+ &view, usage, 0, 0, 0);
map += SURFACE_STATE_ALIGNMENT;
}
fill_buffer_image_param(&image_params[start_slot + i],
img->format, img->u.buf.size);
}
+
+ upload_surface_states(ice->state.surface_uploader, &iv->surface_state);
} else {
pipe_resource_reference(&iv->base.resource, NULL);
- pipe_resource_reference(&iv->surface_state.res, NULL);
+ pipe_resource_reference(&iv->surface_state.ref.res, NULL);
fill_default_image_param(&image_params[start_slot + i]);
}
}
view->res->bind_stages |= 1 << stage;
shs->bound_sampler_views |= 1 << (start + i);
+
+ update_surface_state_addrs(ice->state.surface_uploader,
+ &view->surface_state, view->res->bo);
}
}
{
struct iris_surface *surf = (void *) p_surf;
pipe_resource_reference(&p_surf->texture, NULL);
- pipe_resource_reference(&surf->surface_state.res, NULL);
- pipe_resource_reference(&surf->surface_state_read.res, NULL);
+ pipe_resource_reference(&surf->surface_state.ref.res, NULL);
+ pipe_resource_reference(&surf->surface_state_read.ref.res, NULL);
+ free(surf->surface_state.cpu);
free(surf);
}
info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset + zres->offset;
- info.mocs = mocs(zres->bo, isl_dev);
+ info.mocs = iris_mocs(zres->bo, isl_dev);
view.format = zres->surf.format;
info.stencil_address = stencil_res->bo->gtt_offset + stencil_res->offset;
if (!zres) {
view.format = stencil_res->surf.format;
- info.mocs = mocs(stencil_res->bo, isl_dev);
+ info.mocs = iris_mocs(stencil_res->bo, isl_dev);
}
}
}
value = fui(ice->state.default_inner_level[0]);
} else if (sysval == BRW_PARAM_BUILTIN_TESS_LEVEL_INNER_Y) {
value = fui(ice->state.default_inner_level[1]);
+ } else if (sysval >= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X &&
+ sysval <= BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_Z) {
+ unsigned i = sysval - BRW_PARAM_BUILTIN_WORK_GROUP_SIZE_X;
+ value = ice->state.last_block[i];
} else {
assert(!"unhandled system value");
}
vb.AddressModifyEnable = true;
vb.BufferPitch = buffer->stride;
if (res) {
- vb.BufferSize = res->bo->size - (int) buffer->buffer_offset;
+ vb.BufferSize = res->base.width0 - (int) buffer->buffer_offset;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
- vb.MOCS = mocs(res->bo, &screen->isl_dev);
+ vb.MOCS = iris_mocs(res->bo, &screen->isl_dev);
} else {
vb.NullVertexBuffer = true;
}
sob.SOBufferEnable = true;
sob.StreamOffsetWriteEnable = true;
sob.StreamOutputBufferOffsetAddressEnable = true;
- sob.MOCS = mocs(res->bo, &screen->isl_dev);
+ sob.MOCS = iris_mocs(res->bo, &screen->isl_dev);
sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
sob.StreamOffset = offset;
/* XXX: this should be generated when putting programs in place */
- for (int fs_attr = 0; fs_attr < VARYING_SLOT_MAX; fs_attr++) {
+ for (uint8_t idx = 0; idx < wm_prog_data->urb_setup_attribs_count; idx++) {
+ const uint8_t fs_attr = wm_prog_data->urb_setup_attribs[idx];
const int input_index = wm_prog_data->urb_setup[fs_attr];
if (input_index < 0 || input_index >= 16)
continue;
iris_populate_vs_key(const struct iris_context *ice,
const struct shader_info *info,
gl_shader_stage last_stage,
- struct brw_vs_prog_key *key)
+ struct iris_vs_prog_key *key)
{
const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
if (info->clip_distance_array_size == 0 &&
(info->outputs_written & (VARYING_BIT_POS | VARYING_BIT_CLIP_VERTEX)) &&
last_stage == MESA_SHADER_VERTEX)
- key->nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
+ key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
}
/**
*/
static void
iris_populate_tcs_key(const struct iris_context *ice,
- struct brw_tcs_prog_key *key)
+ struct iris_tcs_prog_key *key)
{
}
iris_populate_tes_key(const struct iris_context *ice,
const struct shader_info *info,
gl_shader_stage last_stage,
- struct brw_tes_prog_key *key)
+ struct iris_tes_prog_key *key)
{
const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
if (info->clip_distance_array_size == 0 &&
(info->outputs_written & (VARYING_BIT_POS | VARYING_BIT_CLIP_VERTEX)) &&
last_stage == MESA_SHADER_TESS_EVAL)
- key->nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
+ key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
}
/**
iris_populate_gs_key(const struct iris_context *ice,
const struct shader_info *info,
gl_shader_stage last_stage,
- struct brw_gs_prog_key *key)
+ struct iris_gs_prog_key *key)
{
const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
if (info->clip_distance_array_size == 0 &&
(info->outputs_written & (VARYING_BIT_POS | VARYING_BIT_CLIP_VERTEX)) &&
last_stage == MESA_SHADER_GEOMETRY)
- key->nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
+ key->vue.nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
}
/**
static void
iris_populate_fs_key(const struct iris_context *ice,
const struct shader_info *info,
- struct brw_wm_prog_key *key)
+ struct iris_fs_prog_key *key)
{
struct iris_screen *screen = (void *) ice->ctx.screen;
const struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
static void
iris_populate_cs_key(const struct iris_context *ice,
- struct brw_cs_prog_key *key)
+ struct iris_cs_prog_key *key)
{
}
return iris_bo_offset_from_base_address(res->bo) + shader->assembly.offset;
}
-/* Gen11 workaround table #2056 WABTPPrefetchDisable suggests to disable
- * prefetching of binding tables in A0 and B0 steppings. XXX: Revisit
- * this WA on C0 stepping.
- *
- * TODO: Fill out SamplerCount for prefetching?
- */
-
#define INIT_THREAD_DISPATCH_FIELDS(pkt, prefix, stage) \
pkt.KernelStartPointer = KSP(shader); \
- pkt.BindingTableEntryCount = GEN_GEN == 11 ? 0 : \
- shader->bt.size_bytes / 4; \
+ pkt.BindingTableEntryCount = shader->bt.size_bytes / 4; \
pkt.FloatingPointMode = prog_data->use_alt_mode; \
\
pkt.DispatchGRFStartRegisterForURBData = \
iris_pack_command(GENX(3DSTATE_HS), shader->derived_data, hs) {
INIT_THREAD_DISPATCH_FIELDS(hs, Vertex, MESA_SHADER_TESS_CTRL);
+#if GEN_GEN >= 12
+ /* GEN:BUG:1604578095:
+ *
+ * Hang occurs when the number of max threads is less than 2 times
+ * the number of instance count. The number of max threads must be
+ * more than 2 times the number of instance count.
+ */
+ assert((devinfo->max_tcs_threads / 2) > tcs_prog_data->instances);
+ hs.DispatchGRFStartRegisterForURBData = prog_data->dispatch_grf_start_reg & 0x1f;
+ hs.DispatchGRFStartRegisterForURBData5 = prog_data->dispatch_grf_start_reg >> 5;
+#endif
+
hs.InstanceCount = tcs_prog_data->instances - 1;
hs.MaximumNumberofThreads = devinfo->max_tcs_threads - 1;
hs.IncludeVertexHandles = true;
+#if GEN_GEN == 12
+ /* Patch Count threshold specifies the maximum number of patches that
+ * will be accumulated before a thread dispatch is forced.
+ */
+ hs.PatchCountThreshold = tcs_prog_data->patch_count_threshold;
+#endif
+
#if GEN_GEN >= 9
hs.DispatchMode = vue_prog_data->dispatch_mode;
hs.IncludePrimitiveID = tcs_prog_data->include_primitive_id;
iris_pack_command(GENX(3DSTATE_PS), ps_state, ps) {
ps.VectorMaskEnable = true;
- // XXX: WABTPPrefetchDisable, see above, drop at C0
- ps.BindingTableEntryCount = GEN_GEN == 11 ? 0 :
- shader->bt.size_bytes / 4;
+ ps.BindingTableEntryCount = shader->bt.size_bytes / 4;
ps.FloatingPointMode = prog_data->use_alt_mode;
ps.MaximumNumberofThreadsPerPSD = 64 - (GEN_GEN == 8 ? 2 : 1);
iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), map, desc) {
desc.KernelStartPointer = KSP(shader);
desc.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs;
- desc.NumberofThreadsinGPGPUThreadGroup = cs_prog_data->threads;
desc.SharedLocalMemorySize =
encode_slm_size(GEN_GEN, prog_data->total_shared);
desc.BarrierEnable = cs_prog_data->uses_barrier;
desc.CrossThreadConstantDataReadLength =
cs_prog_data->push.cross_thread.regs;
+#if GEN_GEN >= 12
+ /* TODO: Check if we are missing workarounds and enable mid-thread
+ * preemption.
+ *
+ * We still have issues with mid-thread preemption (it was already
+ * disabled by the kernel on gen11, due to missing workarounds). It's
+ * possible that we are just missing some workarounds, and could enable
+ * it later, but for now let's disable it to fix a GPU in compute in Car
+ * Chase (and possibly more).
+ */
+ desc.ThreadPreemptionDisable = true;
+#endif
}
}
update_clear_value(struct iris_context *ice,
struct iris_batch *batch,
struct iris_resource *res,
- struct iris_state_ref *state,
+ struct iris_surface_state *surf_state,
unsigned all_aux_modes,
struct isl_view *view)
{
while (aux_modes) {
enum isl_aux_usage aux_usage = u_bit_scan(&aux_modes);
- surf_state_update_clear_value(batch, res, state, all_aux_modes,
- aux_usage);
+ surf_state_update_clear_value(batch, res, &surf_state->ref,
+ all_aux_modes, aux_usage);
}
#elif GEN_GEN == 8
- pipe_resource_reference(&state->res, NULL);
+ /* TODO: Could update rather than re-filling */
+ alloc_surface_states(surf_state, all_aux_modes);
+
+ void *map = surf_state->cpu;
- void *map = alloc_surface_states(ice->state.surface_uploader,
- state, all_aux_modes);
while (aux_modes) {
enum isl_aux_usage aux_usage = u_bit_scan(&aux_modes);
- fill_surface_state(isl_dev, map, res, &res->surf, view, aux_usage, 0, 0);
+ fill_surface_state(isl_dev, map, res, &res->surf, view, aux_usage,
+ 0, 0, 0);
map += SURFACE_STATE_ALIGNMENT;
}
+
+ upload_surface_states(ice->state.surface_uploader, surf_state);
#endif
}
iris_use_pinned_bo(batch, iris_resource_bo(p_surf->texture), writeable);
if (GEN_GEN == 8 && is_read_surface) {
- iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state_read.res), false);
+ iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state_read.ref.res), false);
} else {
- iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state.res), false);
+ iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state.ref.res), false);
}
if (res->aux.bo) {
}
}
- offset = (GEN_GEN == 8 && is_read_surface) ? surf->surface_state_read.offset
- : surf->surface_state.offset;
+ offset = (GEN_GEN == 8 && is_read_surface)
+ ? surf->surface_state_read.ref.offset
+ : surf->surface_state.ref.offset;
return offset +
surf_state_offset_for_aux(res, res->aux.possible_usages, aux_usage);
struct iris_batch *batch,
struct iris_sampler_view *isv)
{
- // XXX: ASTC hacks
enum isl_aux_usage aux_usage =
- iris_resource_texture_aux_usage(ice, isv->res, isv->view.format, 0);
+ iris_resource_texture_aux_usage(ice, isv->res, isv->view.format);
iris_use_pinned_bo(batch, isv->res->bo, false);
- iris_use_pinned_bo(batch, iris_resource_bo(isv->surface_state.res), false);
+ iris_use_pinned_bo(batch, iris_resource_bo(isv->surface_state.ref.res), false);
if (isv->res->aux.bo) {
iris_use_pinned_bo(batch, isv->res->aux.bo, false);
}
}
- return isv->surface_state.offset +
+ return isv->surface_state.ref.offset +
surf_state_offset_for_aux(isv->res, isv->res->aux.sampler_usages,
aux_usage);
}
static uint32_t
use_image(struct iris_batch *batch, struct iris_context *ice,
- struct iris_shader_state *shs, int i)
+ struct iris_shader_state *shs, const struct shader_info *info,
+ int i)
{
struct iris_image_view *iv = &shs->image[i];
struct iris_resource *res = (void *) iv->base.resource;
bool write = iv->base.shader_access & PIPE_IMAGE_ACCESS_WRITE;
iris_use_pinned_bo(batch, res->bo, write);
- iris_use_pinned_bo(batch, iris_resource_bo(iv->surface_state.res), false);
+ iris_use_pinned_bo(batch, iris_resource_bo(iv->surface_state.ref.res), false);
if (res->aux.bo)
iris_use_pinned_bo(batch, res->aux.bo, write);
- return iv->surface_state.offset;
+ enum isl_aux_usage aux_usage =
+ iris_image_view_aux_usage(ice, &iv->base, info);
+
+ return iv->surface_state.ref.offset +
+ surf_state_offset_for_aux(res, res->aux.possible_usages, aux_usage);
}
#define push_bt_entry(addr) \
}
foreach_surface_used(i, IRIS_SURFACE_GROUP_IMAGE) {
- uint32_t addr = use_image(batch, ice, shs, i);
+ uint32_t addr = use_image(batch, ice, shs, info, i);
push_bt_entry(addr);
}
flush_before_state_base_change(batch);
+#if GEN_GEN == 12
+ /* GEN:BUG:1607854226:
+ *
+ * Workaround the non pipelined state not applying in MEDIA/GPGPU pipeline
+ * mode by putting the pipeline temporarily in 3D mode..
+ */
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ emit_pipeline_select(batch, _3D);
+#endif
+
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
sba.SurfaceStateBaseAddressModifyEnable = true;
sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
#endif
}
+#if GEN_GEN == 12
+ /* GEN:BUG:1607854226:
+ *
+ * Put the pipeline back into compute mode.
+ */
+ if (batch->name == IRIS_BATCH_COMPUTE)
+ emit_pipeline_select(batch, GPGPU);
+#endif
+
flush_after_state_base_change(batch);
batch->last_surface_base_address = binder->bo->gtt_offset;
#if GEN_GEN >= 12
void
-genX(emit_aux_map_state)(struct iris_batch *batch)
+genX(invalidate_aux_map_state)(struct iris_batch *batch)
{
struct iris_screen *screen = batch->screen;
void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
return;
uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx);
if (batch->last_aux_map_state != aux_map_state_num) {
+ /* HSD 1209978178: docs say that before programming the aux table:
+ *
+ * "Driver must ensure that the engine is IDLE but ensure it doesn't
+ * add extra flushes in the case it knows that the engine is already
+ * IDLE."
+ *
+ * An end of pipe sync is needed here, otherwise we see GPU hangs in
+ * dEQP-GLES31.functional.copy_image.* tests.
+ */
+ iris_emit_end_of_pipe_sync(batch, "Invalidate aux map table",
+ PIPE_CONTROL_CS_STALL);
+
/* If the aux-map state number increased, then we need to rewrite the
* register. Rewriting the register is used to both set the aux-map
* translation table address, and also to invalidate any previously
* cached translations.
*/
- uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
- assert(base_addr != 0 && ALIGN(base_addr, 32 * 1024) == base_addr);
- iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num),
- base_addr);
+ iris_load_register_imm32(batch, GENX(GFX_CCS_AUX_INV_num), 1);
batch->last_aux_map_state = aux_map_state_num;
}
}
+
+static void
+init_aux_map_state(struct iris_batch *batch)
+{
+ struct iris_screen *screen = batch->screen;
+ void *aux_map_ctx = iris_bufmgr_get_aux_map_context(screen->bufmgr);
+ if (!aux_map_ctx)
+ return;
+
+ uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx);
+ assert(base_addr != 0 && align64(base_addr, 32 * 1024) == base_addr);
+ iris_load_register_imm64(batch, GENX(GFX_AUX_TABLE_BASE_ADDR_num),
+ base_addr);
+}
+#endif
+
+struct push_bos {
+ struct {
+ struct iris_address addr;
+ uint32_t length;
+ } buffers[4];
+ int buffer_count;
+ uint32_t max_length;
+};
+
+static void
+setup_constant_buffers(struct iris_context *ice,
+ struct iris_batch *batch,
+ int stage,
+ struct push_bos *push_bos)
+{
+ struct iris_shader_state *shs = &ice->state.shaders[stage];
+ struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+ struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
+
+ uint32_t push_range_sum = 0;
+
+ int n = 0;
+ for (int i = 0; i < 4; i++) {
+ const struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
+
+ if (range->length == 0)
+ continue;
+
+ push_range_sum += range->length;
+
+ if (range->length > push_bos->max_length)
+ push_bos->max_length = range->length;
+
+ /* Range block is a binding table index, map back to UBO index. */
+ unsigned block_index = iris_bti_to_group_index(
+ &shader->bt, IRIS_SURFACE_GROUP_UBO, range->block);
+ assert(block_index != IRIS_SURFACE_NOT_USED);
+
+ struct pipe_shader_buffer *cbuf = &shs->constbuf[block_index];
+ struct iris_resource *res = (void *) cbuf->buffer;
+
+ assert(cbuf->buffer_offset % 32 == 0);
+
+ push_bos->buffers[n].length = range->length;
+ push_bos->buffers[n].addr =
+ res ? ro_bo(res->bo, range->start * 32 + cbuf->buffer_offset)
+ : ro_bo(batch->screen->workaround_bo, 0);
+ n++;
+ }
+
+ /* From the 3DSTATE_CONSTANT_XS and 3DSTATE_CONSTANT_ALL programming notes:
+ *
+ * "The sum of all four read length fields must be less than or
+ * equal to the size of 64."
+ */
+ assert(push_range_sum <= 64);
+
+ push_bos->buffer_count = n;
+}
+
+static void
+emit_push_constant_packets(struct iris_context *ice,
+ struct iris_batch *batch,
+ int stage,
+ const struct push_bos *push_bos)
+{
+ UNUSED struct isl_device *isl_dev = &batch->screen->isl_dev;
+ struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+ struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
+
+ iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
+ pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
+#if GEN_GEN >= 12
+ pkt.MOCS = isl_dev->mocs.internal;
+#endif
+ if (prog_data) {
+ /* The Skylake PRM contains the following restriction:
+ *
+ * "The driver must ensure The following case does not occur
+ * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
+ * buffer 3 read length equal to zero committed followed by a
+ * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
+ * zero committed."
+ *
+ * To avoid this, we program the buffers in the highest slots.
+ * This way, slot 0 is only used if slot 3 is also used.
+ */
+ int n = push_bos->buffer_count;
+ assert(n <= 4);
+ const unsigned shift = 4 - n;
+ for (int i = 0; i < n; i++) {
+ pkt.ConstantBody.ReadLength[i + shift] =
+ push_bos->buffers[i].length;
+ pkt.ConstantBody.Buffer[i + shift] = push_bos->buffers[i].addr;
+ }
+ }
+ }
+}
+
+#if GEN_GEN >= 12
+static void
+emit_push_constant_packet_all(struct iris_context *ice,
+ struct iris_batch *batch,
+ uint32_t shader_mask,
+ const struct push_bos *push_bos)
+{
+ struct isl_device *isl_dev = &batch->screen->isl_dev;
+
+ if (!push_bos) {
+ iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_ALL), pc) {
+ pc.ShaderUpdateEnable = shader_mask;
+ }
+ return;
+ }
+
+ const uint32_t n = push_bos->buffer_count;
+ const uint32_t max_pointers = 4;
+ const uint32_t num_dwords = 2 + 2 * n;
+ uint32_t const_all[2 + 2 * max_pointers];
+ uint32_t *dw = &const_all[0];
+
+ assert(n <= max_pointers);
+ iris_pack_command(GENX(3DSTATE_CONSTANT_ALL), dw, all) {
+ all.DWordLength = num_dwords - 2;
+ all.MOCS = isl_dev->mocs.internal;
+ all.ShaderUpdateEnable = shader_mask;
+ all.PointerBufferMask = (1 << n) - 1;
+ }
+ dw += 2;
+
+ for (int i = 0; i < n; i++) {
+ _iris_pack_state(batch, GENX(3DSTATE_CONSTANT_ALL_DATA),
+ dw + i * 2, data) {
+ data.PointerToConstantBuffer = push_bos->buffers[i].addr;
+ data.ConstantBufferReadLength = push_bos->buffers[i].length;
+ }
+ }
+ iris_batch_emit(batch, const_all, sizeof(uint32_t) * num_dwords);
+}
#endif
static void
assert(size[i] != 0);
}
- genX(emit_urb_setup)(ice, batch, size,
- ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
- ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL);
+ unsigned entries[4], start[4];
+ gen_get_urb_config(&batch->screen->devinfo,
+ batch->screen->l3_config_3d,
+ ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
+ ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
+ size, entries, start,
+ &ice->state.urb_deref_block_size);
+
+ for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
+ iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
+ urb._3DCommandSubOpcode += i;
+ urb.VSURBStartingAddress = start[i];
+ urb.VSURBEntryAllocationSize = size[i] - 1;
+ urb.VSNumberofURBEntries = entries[i];
+ }
+ }
}
if (dirty & IRIS_DIRTY_BLEND_STATE) {
}
}
+ /* GEN:BUG:1604061319
+ *
+ * 3DSTATE_CONSTANT_* needs to be programmed before BTP_*
+ *
+ * Testing shows that all the 3DSTATE_CONSTANT_XS need to be emitted if
+ * any stage has a dirty binding table.
+ */
+ const bool emit_const_wa = GEN_GEN >= 11 &&
+ (dirty & IRIS_ALL_DIRTY_BINDINGS) != 0;
+
+#if GEN_GEN >= 12
+ uint32_t nobuffer_stages = 0;
+#endif
+
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
- if (!(dirty & (IRIS_DIRTY_CONSTANTS_VS << stage)))
+ if (!(dirty & (IRIS_DIRTY_CONSTANTS_VS << stage)) &&
+ !emit_const_wa)
continue;
struct iris_shader_state *shs = &ice->state.shaders[stage];
if (shs->sysvals_need_upload)
upload_sysvals(ice, stage);
- struct brw_stage_prog_data *prog_data = (void *) shader->prog_data;
-
- iris_emit_cmd(batch, GENX(3DSTATE_CONSTANT_VS), pkt) {
- pkt._3DCommandSubOpcode = push_constant_opcodes[stage];
- if (prog_data) {
- /* The Skylake PRM contains the following restriction:
- *
- * "The driver must ensure The following case does not occur
- * without a flush to the 3D engine: 3DSTATE_CONSTANT_* with
- * buffer 3 read length equal to zero committed followed by a
- * 3DSTATE_CONSTANT_* with buffer 0 read length not equal to
- * zero committed."
- *
- * To avoid this, we program the buffers in the highest slots.
- * This way, slot 0 is only used if slot 3 is also used.
- */
- int n = 3;
-
- for (int i = 3; i >= 0; i--) {
- const struct brw_ubo_range *range = &prog_data->ubo_ranges[i];
-
- if (range->length == 0)
- continue;
-
- /* Range block is a binding table index, map back to UBO index. */
- unsigned block_index = iris_bti_to_group_index(
- &shader->bt, IRIS_SURFACE_GROUP_UBO, range->block);
- assert(block_index != IRIS_SURFACE_NOT_USED);
+ struct push_bos push_bos = {};
+ setup_constant_buffers(ice, batch, stage, &push_bos);
- struct pipe_shader_buffer *cbuf = &shs->constbuf[block_index];
- struct iris_resource *res = (void *) cbuf->buffer;
-
- assert(cbuf->buffer_offset % 32 == 0);
+#if GEN_GEN >= 12
+ /* If this stage doesn't have any push constants, emit it later in a
+ * single CONSTANT_ALL packet with all the other stages.
+ */
+ if (push_bos.buffer_count == 0) {
+ nobuffer_stages |= 1 << stage;
+ continue;
+ }
- pkt.ConstantBody.ReadLength[n] = range->length;
- pkt.ConstantBody.Buffer[n] =
- res ? ro_bo(res->bo, range->start * 32 + cbuf->buffer_offset)
- : ro_bo(batch->screen->workaround_bo, 0);
- n--;
- }
- }
+ /* The Constant Buffer Read Length field from 3DSTATE_CONSTANT_ALL
+ * contains only 5 bits, so we can only use it for buffers smaller than
+ * 32.
+ */
+ if (push_bos.max_length < 32) {
+ emit_push_constant_packet_all(ice, batch, 1 << stage, &push_bos);
+ continue;
}
+#endif
+ emit_push_constant_packets(ice, batch, stage, &push_bos);
}
+#if GEN_GEN >= 12
+ if (nobuffer_stages)
+ emit_push_constant_packet_all(ice, batch, nobuffer_stages, NULL);
+#endif
+
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
/* Gen9 requires 3DSTATE_BINDING_TABLE_POINTERS_XS to be re-emitted
* in order to commit constants. TODO: Investigate "Disable Gather
ARRAY_SIZE(cso_rast->clip));
}
- if (dirty & IRIS_DIRTY_RASTER) {
+ if (dirty & (IRIS_DIRTY_RASTER | IRIS_DIRTY_URB)) {
struct iris_rasterizer_state *cso = ice->state.cso_rast;
iris_batch_emit(batch, cso->raster, sizeof(cso->raster));
uint32_t dynamic_sf[GENX(3DSTATE_SF_length)];
iris_pack_command(GENX(3DSTATE_SF), &dynamic_sf, sf) {
sf.ViewportTransformEnable = !ice->state.window_space_position;
+
+#if GEN_GEN >= 12
+ sf.DerefBlockSize = ice->state.urb_deref_block_size;
+#endif
}
iris_emit_merge(batch, cso->sf, dynamic_sf,
ARRAY_SIZE(dynamic_sf));
* first.
*/
uint32_t clear_length = GENX(3DSTATE_CLEAR_PARAMS_length) * 4;
- uint32_t cso_z_size = sizeof(cso_z->packets) - clear_length;
+ uint32_t cso_z_size = batch->screen->isl_dev.ds.size - clear_length;;
+
+#if GEN_GEN == 12
+ /* GEN:BUG:14010455700
+ *
+ * ISL will change some CHICKEN registers depending on the depth surface
+ * format, along with emitting the depth and stencil packets. In that
+ * case, we want to do a depth flush and stall, so the pipeline is not
+ * using these settings while we change the registers.
+ */
+ iris_emit_end_of_pipe_sync(batch,
+ "Workaround: Stop pipeline for 14010455700",
+ PIPE_CONTROL_DEPTH_STALL |
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+#endif
+
iris_batch_emit(batch, cso_z->packets, cso_z_size);
if (GEN_GEN >= 12) {
/* GEN:BUG:1408224581
if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
int count = util_bitcount64(ice->state.bound_vertex_buffers);
- int dynamic_bound = ice->state.bound_vertex_buffers;
+ uint64_t dynamic_bound = ice->state.bound_vertex_buffers;
if (ice->state.vs_uses_draw_params) {
assert(ice->draw.draw_params.res);
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.draw_params.offset);
- vb.MOCS = mocs(res->bo, &batch->screen->isl_dev);
+ vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev);
}
dynamic_bound |= 1ull << count;
count++;
vb.BufferStartingAddress =
ro_bo(NULL, res->bo->gtt_offset +
(int) ice->draw.derived_draw_params.offset);
- vb.MOCS = mocs(res->bo, &batch->screen->isl_dev);
+ vb.MOCS = iris_mocs(res->bo, &batch->screen->isl_dev);
}
dynamic_bound |= 1ull << count;
count++;
}
if (count) {
+#if GEN_GEN >= 11
+ /* Gen11+ doesn't need the cache workaround below */
+ uint64_t bound = dynamic_bound;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ iris_use_optional_res(batch, genx->vertex_buffers[i].resource,
+ false);
+ }
+#else
/* The VF cache designers cut corners, and made the cache key's
* <VertexBufferIndex, Memory Address> tuple only consider the bottom
* 32 bits of the address. If you have two vertex buffers which get
"workaround: VF cache 32-bit key [VB]",
flush_flags);
}
+#endif
const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length);
genX(emit_hashing_mode)(ice, batch, UINT_MAX, UINT_MAX, 1);
#if GEN_GEN >= 12
- genX(emit_aux_map_state)(batch);
+ genX(invalidate_aux_map_state)(batch);
#endif
}
uint32_t ib_packet[GENX(3DSTATE_INDEX_BUFFER_length)];
iris_pack_command(GENX(3DSTATE_INDEX_BUFFER), ib_packet, ib) {
ib.IndexFormat = draw->index_size >> 1;
- ib.MOCS = mocs(bo, &batch->screen->isl_dev);
+ ib.MOCS = iris_mocs(bo, &batch->screen->isl_dev);
ib.BufferSize = bo->size - offset;
ib.BufferStartingAddress = ro_bo(NULL, bo->gtt_offset + offset);
}
iris_use_pinned_bo(batch, bo, false);
}
+#if GEN_GEN < 11
/* The VF cache key only uses 32-bits, see vertex buffer comment above */
uint16_t high_bits = bo->gtt_offset >> 32ull;
if (high_bits != ice->state.last_index_bo_high_bits) {
PIPE_CONTROL_CS_STALL);
ice->state.last_index_bo_high_bits = high_bits;
}
+#endif
}
#define _3DPRIM_END_OFFSET 0x2420
struct brw_stage_prog_data *prog_data = shader->prog_data;
struct brw_cs_prog_data *cs_prog_data = (void *) prog_data;
+ const uint32_t group_size = grid->block[0] * grid->block[1] * grid->block[2];
+ const unsigned threads = DIV_ROUND_UP(group_size, cs_prog_data->simd_size);
+
/* Always pin the binder. If we're emitting new binding table pointers,
* we need it. If not, we're probably inheriting old tables via the
* context, and need it anyway. Since true zero-bindings cases are
iris_use_pinned_bo(batch, ice->state.border_color_pool.bo, false);
#if GEN_GEN >= 12
- genX(emit_aux_map_state)(batch);
+ genX(invalidate_aux_map_state)(batch);
#endif
if (dirty & IRIS_DIRTY_CS) {
vfe.URBEntryAllocationSize = 2;
vfe.CURBEAllocationSize =
- ALIGN(cs_prog_data->push.per_thread.regs * cs_prog_data->threads +
+ ALIGN(cs_prog_data->push.per_thread.regs * threads +
cs_prog_data->push.cross_thread.regs, 2);
}
}
assert(cs_prog_data->push.cross_thread.dwords == 0 &&
cs_prog_data->push.per_thread.dwords == 1 &&
cs_prog_data->base.param[0] == BRW_PARAM_BUILTIN_SUBGROUP_ID);
+ const unsigned push_const_size =
+ brw_cs_push_const_total_size(cs_prog_data, threads);
uint32_t *curbe_data_map =
stream_state(batch, ice->state.dynamic_uploader,
&ice->state.last_res.cs_thread_ids,
- ALIGN(cs_prog_data->push.total.size, 64), 64,
+ ALIGN(push_const_size, 64), 64,
&curbe_data_offset);
assert(curbe_data_map);
- memset(curbe_data_map, 0x5a, ALIGN(cs_prog_data->push.total.size, 64));
- iris_fill_cs_push_const_buffer(cs_prog_data, curbe_data_map);
+ memset(curbe_data_map, 0x5a, ALIGN(push_const_size, 64));
+ iris_fill_cs_push_const_buffer(cs_prog_data, threads, curbe_data_map);
iris_emit_cmd(batch, GENX(MEDIA_CURBE_LOAD), curbe) {
- curbe.CURBETotalDataLength =
- ALIGN(cs_prog_data->push.total.size, 64);
+ curbe.CURBETotalDataLength = ALIGN(push_const_size, 64);
curbe.CURBEDataStartAddress = curbe_data_offset;
}
}
iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), desc, idd) {
idd.SamplerStatePointer = shs->sampler_table.offset;
idd.BindingTablePointer = binder->bt_offset[MESA_SHADER_COMPUTE];
+ idd.NumberofThreadsinGPGPUThreadGroup = threads;
}
for (int i = 0; i < GENX(INTERFACE_DESCRIPTOR_DATA_length); i++)
}
}
- uint32_t group_size = grid->block[0] * grid->block[1] * grid->block[2];
uint32_t remainder = group_size & (cs_prog_data->simd_size - 1);
uint32_t right_mask;
ggw.SIMDSize = cs_prog_data->simd_size / 16;
ggw.ThreadDepthCounterMaximum = 0;
ggw.ThreadHeightCounterMaximum = 0;
- ggw.ThreadWidthCounterMaximum = cs_prog_data->threads - 1;
+ ggw.ThreadWidthCounterMaximum = threads - 1;
ggw.ThreadGroupIDXDimension = grid->grid[0];
ggw.ThreadGroupIDYDimension = grid->grid[1];
ggw.ThreadGroupIDZDimension = grid->grid[2];
}
for (int i = 0; i < PIPE_MAX_SHADER_IMAGES; i++) {
pipe_resource_reference(&shs->image[i].base.resource, NULL);
- pipe_resource_reference(&shs->image[i].surface_state.res, NULL);
+ pipe_resource_reference(&shs->image[i].surface_state.ref.res, NULL);
+ free(shs->image[i].surface_state.cpu);
}
for (int i = 0; i < PIPE_MAX_SHADER_BUFFERS; i++) {
pipe_resource_reference(&shs->ssbo[i].buffer, NULL);
static void
iris_rebind_buffer(struct iris_context *ice,
- struct iris_resource *res,
- uint64_t old_address)
+ struct iris_resource *res)
{
struct pipe_context *ctx = &ice->ctx;
- struct iris_screen *screen = (void *) ctx->screen;
struct iris_genx_state *genx = ice->state.genx;
assert(res->base.target == PIPE_BUFFER);
STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_start) == 32);
STATIC_ASSERT(GENX(VERTEX_BUFFER_STATE_BufferStartingAddress_bits) == 64);
uint64_t *addr = (uint64_t *) &state->state[1];
+ struct iris_bo *bo = iris_resource_bo(state->resource);
- if (*addr == old_address + state->offset) {
- *addr = res->bo->gtt_offset + state->offset;
+ if (*addr != bo->gtt_offset + state->offset) {
+ *addr = bo->gtt_offset + state->offset;
ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
}
}
while (bound_sampler_views) {
const int i = u_bit_scan(&bound_sampler_views);
struct iris_sampler_view *isv = shs->textures[i];
+ struct iris_bo *bo = isv->res->bo;
- if (res->bo == iris_resource_bo(isv->base.texture)) {
- void *map = alloc_surface_states(ice->state.surface_uploader,
- &isv->surface_state,
- isv->res->aux.sampler_usages);
- assert(map);
- fill_buffer_surface_state(&screen->isl_dev, isv->res, map,
- isv->view.format, isv->view.swizzle,
- isv->base.u.buf.offset,
- isv->base.u.buf.size);
+ if (update_surface_state_addrs(ice->state.surface_uploader,
+ &isv->surface_state, bo)) {
ice->state.dirty |= IRIS_DIRTY_BINDINGS_VS << s;
}
}
while (bound_image_views) {
const int i = u_bit_scan(&bound_image_views);
struct iris_image_view *iv = &shs->image[i];
+ struct iris_bo *bo = iris_resource_bo(iv->base.resource);
- if (res->bo == iris_resource_bo(iv->base.resource)) {
- iris_set_shader_images(ctx, p_stage, i, 1, &iv->base);
+ if (update_surface_state_addrs(ice->state.surface_uploader,
+ &iv->surface_state, bo)) {
+ ice->state.dirty |= IRIS_DIRTY_BINDINGS_VS << s;
}
}
}
0, NULL, 0, 0);
}
- if (GEN_GEN == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
+ /* GEN:BUG:1409226450, Wait for EU to be idle before pipe control which
+ * invalidates the instruction cache
+ */
+ if (GEN_GEN == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
+ iris_emit_raw_pipe_control(batch,
+ "workaround: CS stall before instruction "
+ "cache invalidate",
+ PIPE_CONTROL_CS_STALL |
+ PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
+ imm);
+ }
+
+ if ((GEN_GEN == 9 || (GEN_GEN == 12 && devinfo->revision == 0 /* A0*/)) &&
+ IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
/* Project: SKL / Argument: LRI Post Sync Operation [23]
*
* "PIPECONTROL command with “Command Streamer Stall Enable” must be
* PIPELINE_SELECT command is set to GPGPU mode of operation)."
*
* The same text exists a few rows below for Post Sync Op.
+ *
+ * On Gen12 this is GEN:BUG:1607156449.
*/
iris_emit_raw_pipe_control(batch,
"workaround: CS stall before gpgpu post-sync",
PIPE_CONTROL_CS_STALL, bo, offset, imm);
}
- if (GEN_GEN == 10 && (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH)) {
- /* Cannonlake:
- * "Before sending a PIPE_CONTROL command with bit 12 set, SW must issue
- * another PIPE_CONTROL with Render Target Cache Flush Enable (bit 12)
- * = 0 and Pipe Control Flush Enable (bit 7) = 1"
- */
- iris_emit_raw_pipe_control(batch,
- "workaround: PC flush before RT flush",
- PIPE_CONTROL_FLUSH_ENABLE, bo, offset, imm);
- }
-
/* "Flush Types" workarounds ---------------------------------------------
* We do these now because they may add post-sync operations or CS stalls.
*/
}
}
- /* #1130 from Gen10 workarounds page:
- *
- * "Enable Depth Stall on every Post Sync Op if Render target Cache
- * Flush is not enabled in same PIPE CONTROL and Enable Pixel score
- * board stall if Render target cache flush is enabled."
- *
- * Applicable to CNL B0 and C0 steppings only.
- *
- * The wording here is unclear, and this workaround doesn't look anything
- * like the internal bug report recommendations, but leave it be for now...
- */
- if (GEN_GEN == 10) {
- if (flags & PIPE_CONTROL_RENDER_TARGET_FLUSH) {
- flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
- } else if (flags & non_lri_post_sync_flags) {
- flags |= PIPE_CONTROL_DEPTH_STALL;
- }
- }
-
if (flags & PIPE_CONTROL_DEPTH_STALL) {
/* From the PIPE_CONTROL instruction table, bit 13 (Depth Stall Enable):
*
flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
}
+ if (GEN_GEN >= 12 && (flags & PIPE_CONTROL_DEPTH_CACHE_FLUSH)) {
+ /* GEN:BUG:1409600907:
+ *
+ * "PIPE_CONTROL with Depth Stall Enable bit must be set
+ * with any PIPE_CONTROL with Depth Flush Enable bit set.
+ */
+ flags |= PIPE_CONTROL_DEPTH_STALL;
+ }
+
/* Emit --------------------------------------------------------------- */
if (INTEL_DEBUG & DEBUG_PIPE_CONTROL) {
fprintf(stderr,
- " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
+ " PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
(flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "",
(flags & PIPE_CONTROL_CS_STALL) ? "CS " : "",
(flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "",
(flags & PIPE_CONTROL_WRITE_IMMEDIATE) ? "WriteImm " : "",
(flags & PIPE_CONTROL_WRITE_DEPTH_COUNT) ? "WriteZCount " : "",
(flags & PIPE_CONTROL_WRITE_TIMESTAMP) ? "WriteTimestamp " : "",
+ (flags & PIPE_CONTROL_FLUSH_HDC) ? "HDC " : "",
imm, reason);
}
iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {
#if GEN_GEN >= 12
pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH;
+#endif
+#if GEN_GEN >= 11
+ pc.HDCPipelineFlushEnable = flags & PIPE_CONTROL_FLUSH_HDC;
#endif
pc.LRIPostSyncOperation = NoLRIOperation;
pc.PipeControlFlushEnable = flags & PIPE_CONTROL_FLUSH_ENABLE;
}
}
-void
-genX(emit_urb_setup)(struct iris_context *ice,
- struct iris_batch *batch,
- const unsigned size[4],
- bool tess_present, bool gs_present)
-{
- const struct gen_device_info *devinfo = &batch->screen->devinfo;
- const unsigned push_size_kB = 32;
- unsigned entries[4];
- unsigned start[4];
-
- ice->shaders.last_vs_entry_size = size[MESA_SHADER_VERTEX];
-
- gen_get_urb_config(devinfo, 1024 * push_size_kB,
- 1024 * ice->shaders.urb_size,
- tess_present, gs_present,
- size, entries, start);
-
- for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
- iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
- urb._3DCommandSubOpcode += i;
- urb.VSURBStartingAddress = start[i];
- urb.VSURBEntryAllocationSize = size[i] - 1;
- urb.VSNumberofURBEntries = entries[i];
- }
- }
-}
-
#if GEN_GEN == 9
/**
* Preemption on Gen9 has to be enabled or disabled in various cases.
#endif
}
+static void
+iris_set_frontend_noop(struct pipe_context *ctx, bool enable)
+{
+ struct iris_context *ice = (struct iris_context *) ctx;
+
+ ice->state.dirty |= iris_batch_prepare_noop(&ice->batches[IRIS_BATCH_RENDER],
+ enable,
+ IRIS_ALL_DIRTY_FOR_RENDER);
+ ice->state.dirty |= iris_batch_prepare_noop(&ice->batches[IRIS_BATCH_COMPUTE],
+ enable,
+ IRIS_ALL_DIRTY_FOR_COMPUTE);
+}
+
void
genX(init_state)(struct iris_context *ice)
{
ctx->create_stream_output_target = iris_create_stream_output_target;
ctx->stream_output_target_destroy = iris_stream_output_target_destroy;
ctx->set_stream_output_targets = iris_set_stream_output_targets;
-
- ice->vtbl.destroy_state = iris_destroy_state;
- ice->vtbl.init_render_context = iris_init_render_context;
- ice->vtbl.init_compute_context = iris_init_compute_context;
- ice->vtbl.upload_render_state = iris_upload_render_state;
- ice->vtbl.update_surface_base_address = iris_update_surface_base_address;
- ice->vtbl.upload_compute_state = iris_upload_compute_state;
- ice->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
- ice->vtbl.emit_mi_report_perf_count = iris_emit_mi_report_perf_count;
- ice->vtbl.rebind_buffer = iris_rebind_buffer;
- ice->vtbl.load_register_reg32 = iris_load_register_reg32;
- ice->vtbl.load_register_reg64 = iris_load_register_reg64;
- ice->vtbl.load_register_imm32 = iris_load_register_imm32;
- ice->vtbl.load_register_imm64 = iris_load_register_imm64;
- ice->vtbl.load_register_mem32 = iris_load_register_mem32;
- ice->vtbl.load_register_mem64 = iris_load_register_mem64;
- ice->vtbl.store_register_mem32 = iris_store_register_mem32;
- ice->vtbl.store_register_mem64 = iris_store_register_mem64;
- ice->vtbl.store_data_imm32 = iris_store_data_imm32;
- ice->vtbl.store_data_imm64 = iris_store_data_imm64;
- ice->vtbl.copy_mem_mem = iris_copy_mem_mem;
- ice->vtbl.derived_program_state_size = iris_derived_program_state_size;
- ice->vtbl.store_derived_program_state = iris_store_derived_program_state;
- ice->vtbl.create_so_decl_list = iris_create_so_decl_list;
- ice->vtbl.populate_vs_key = iris_populate_vs_key;
- ice->vtbl.populate_tcs_key = iris_populate_tcs_key;
- ice->vtbl.populate_tes_key = iris_populate_tes_key;
- ice->vtbl.populate_gs_key = iris_populate_gs_key;
- ice->vtbl.populate_fs_key = iris_populate_fs_key;
- ice->vtbl.populate_cs_key = iris_populate_cs_key;
- ice->vtbl.mocs = mocs;
- ice->vtbl.lost_genx_state = iris_lost_genx_state;
+ ctx->set_frontend_noop = iris_set_frontend_noop;
+
+ screen->vtbl.destroy_state = iris_destroy_state;
+ screen->vtbl.init_render_context = iris_init_render_context;
+ screen->vtbl.init_compute_context = iris_init_compute_context;
+ screen->vtbl.upload_render_state = iris_upload_render_state;
+ screen->vtbl.update_surface_base_address = iris_update_surface_base_address;
+ screen->vtbl.upload_compute_state = iris_upload_compute_state;
+ screen->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
+ screen->vtbl.emit_mi_report_perf_count = iris_emit_mi_report_perf_count;
+ screen->vtbl.rebind_buffer = iris_rebind_buffer;
+ screen->vtbl.load_register_reg32 = iris_load_register_reg32;
+ screen->vtbl.load_register_reg64 = iris_load_register_reg64;
+ screen->vtbl.load_register_imm32 = iris_load_register_imm32;
+ screen->vtbl.load_register_imm64 = iris_load_register_imm64;
+ screen->vtbl.load_register_mem32 = iris_load_register_mem32;
+ screen->vtbl.load_register_mem64 = iris_load_register_mem64;
+ screen->vtbl.store_register_mem32 = iris_store_register_mem32;
+ screen->vtbl.store_register_mem64 = iris_store_register_mem64;
+ screen->vtbl.store_data_imm32 = iris_store_data_imm32;
+ screen->vtbl.store_data_imm64 = iris_store_data_imm64;
+ screen->vtbl.copy_mem_mem = iris_copy_mem_mem;
+ screen->vtbl.derived_program_state_size = iris_derived_program_state_size;
+ screen->vtbl.store_derived_program_state = iris_store_derived_program_state;
+ screen->vtbl.create_so_decl_list = iris_create_so_decl_list;
+ screen->vtbl.populate_vs_key = iris_populate_vs_key;
+ screen->vtbl.populate_tcs_key = iris_populate_tcs_key;
+ screen->vtbl.populate_tes_key = iris_populate_tes_key;
+ screen->vtbl.populate_gs_key = iris_populate_gs_key;
+ screen->vtbl.populate_fs_key = iris_populate_fs_key;
+ screen->vtbl.populate_cs_key = iris_populate_cs_key;
+ screen->vtbl.lost_genx_state = iris_lost_genx_state;
ice->state.dirty = ~0ull;
projects / mesa.git / blobdiff