}
}
+static void
+iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
+ bool has_slm, bool wants_dc_cache)
+{
+ uint32_t reg_val;
+ iris_pack_state(GENX(L3CNTLREG), ®_val, reg) {
+ reg.SLMEnable = has_slm;
+#if GEN_GEN == 11
+ /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+ * in L3CNTLREG register. The default setting of the bit is not the
+ * desirable behavior.
+ */
+ reg.ErrorDetectionBehaviorControl = true;
+#endif
+ reg.URBAllocation = cfg->n[GEN_L3P_URB];
+ reg.ROAllocation = cfg->n[GEN_L3P_RO];
+ reg.DCAllocation = cfg->n[GEN_L3P_DC];
+ reg.AllAllocation = cfg->n[GEN_L3P_ALL];
+ }
+ iris_emit_lri(batch, L3CNTLREG, reg_val);
+}
+
+static void
+iris_emit_default_l3_config(struct iris_batch *batch,
+ const struct gen_device_info *devinfo,
+ bool compute)
+{
+ bool wants_dc_cache = true;
+ bool has_slm = compute;
+ const struct gen_l3_weights w =
+ gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
+ const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
+ iris_emit_l3_config(batch, cfg, has_slm, wants_dc_cache);
+}
+
/**
* Upload the initial GPU state for a render context.
*
emit_pipeline_select(batch, _3D);
+ iris_emit_default_l3_config(batch, devinfo, false);
+
init_state_base_address(batch);
#if GEN_GEN >= 9
emit_pipeline_select(batch, GPGPU);
- const bool has_slm = true;
- const bool wants_dc_cache = true;
-
- const struct gen_l3_weights w =
- gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
- const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
-
- uint32_t reg_val;
- iris_pack_state(GENX(L3CNTLREG), ®_val, reg) {
- reg.SLMEnable = has_slm;
-#if GEN_GEN == 11
- /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
- * in L3CNTLREG register. The default setting of the bit is not the
- * desirable behavior.
- */
- reg.ErrorDetectionBehaviorControl = true;
-#endif
- reg.URBAllocation = cfg->n[GEN_L3P_URB];
- reg.ROAllocation = cfg->n[GEN_L3P_RO];
- reg.DCAllocation = cfg->n[GEN_L3P_DC];
- reg.AllAllocation = cfg->n[GEN_L3P_ALL];
- }
- iris_emit_lri(batch, L3CNTLREG, reg_val);
+ iris_emit_default_l3_config(batch, devinfo, true);
init_state_base_address(batch);
/** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
uint8_t blend_enables;
+
+ /** Bitfield of whether color writes are enabled for RT[i] */
+ uint8_t color_write_enables;
};
static enum pipe_blendfactor
uint32_t *blend_entry = cso->blend_state + GENX(BLEND_STATE_length);
cso->blend_enables = 0;
+ cso->color_write_enables = 0;
STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS <= 8);
cso->alpha_to_coverage = state->alpha_to_coverage;
if (rt->blend_enable)
cso->blend_enables |= 1u << i;
+ if (rt->colormask)
+ cso->color_write_enables |= 1u << i;
+
iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_entry, be) {
be.LogicOpEnable = state->logicop_enable;
be.LogicOpFunction = state->logicop_func;
ice->state.dirty |= ice->state.dirty_for_nos[IRIS_NOS_BLEND];
}
+/**
+ * Return true if the FS writes to any color outputs which are not disabled
+ * via color masking.
+ */
+static bool
+has_writeable_rt(const struct iris_blend_state *cso_blend,
+ const struct shader_info *fs_info)
+{
+ if (!fs_info)
+ return false;
+
+ unsigned rt_outputs = fs_info->outputs_written >> FRAG_RESULT_DATA0;
+
+ if (fs_info->outputs_written & BITFIELD64_BIT(FRAG_RESULT_COLOR))
+ rt_outputs = (1 << BRW_MAX_DRAW_BUFFERS) - 1;
+
+ return cso_blend->color_write_enables & rt_outputs;
+}
+
/**
* Gallium CSO for depth, stencil, and alpha testing state.
*/
.mocs = mocs(bo));
}
+#define SURFACE_STATE_ALIGNMENT 64
+
/**
- * Allocate a SURFACE_STATE structure.
+ * Allocate several contiguous SURFACE_STATE structures, one for each
+ * supported auxiliary surface mode.
*/
static void *
alloc_surface_states(struct u_upload_mgr *mgr,
- struct iris_state_ref *ref)
+ struct iris_state_ref *ref,
+ unsigned aux_usages)
{
const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length);
- void *map = upload_state(mgr, ref, surf_size, 64);
+ /* If this changes, update this to explicitly align pointers */
+ STATIC_ASSERT(surf_size == SURFACE_STATE_ALIGNMENT);
+
+ assert(aux_usages != 0);
+
+ void *map =
+ upload_state(mgr, ref, util_bitcount(aux_usages) * surf_size,
+ SURFACE_STATE_ALIGNMENT);
ref->offset += iris_bo_offset_from_base_address(iris_resource_bo(ref->res));
fill_surface_state(struct isl_device *isl_dev,
void *map,
struct iris_resource *res,
- struct isl_view *view)
+ struct isl_view *view,
+ unsigned aux_usage)
{
struct isl_surf_fill_state_info f = {
.surf = &res->surf,
.address = res->bo->gtt_offset,
};
+ if (aux_usage != ISL_AUX_USAGE_NONE) {
+ f.aux_surf = &res->aux.surf;
+ f.aux_usage = aux_usage;
+ f.aux_address = res->aux.bo->gtt_offset + res->aux.offset;
+ // XXX: clear color
+ }
+
isl_surf_fill_state_s(isl_dev, map, &f);
}
pipe_reference_init(&isv->base.reference, 1);
pipe_resource_reference(&isv->base.texture, tex);
- void *map = alloc_surface_states(ice->state.surface_uploader,
- &isv->surface_state);
- if (!unlikely(map))
- return NULL;
-
if (util_format_is_depth_or_stencil(tmpl->format)) {
struct iris_resource *zres, *sres;
const struct util_format_description *desc =
isv->res = (struct iris_resource *) tex;
+ void *map = alloc_surface_states(ice->state.surface_uploader,
+ &isv->surface_state,
+ isv->res->aux.possible_usages);
+ if (!unlikely(map))
+ return NULL;
+
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_TEXTURE_BIT;
if (isv->base.target == PIPE_TEXTURE_CUBE ||
isv->view.array_len =
tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1;
- fill_surface_state(&screen->isl_dev, map, isv->res, &isv->view);
+ unsigned aux_modes = isv->res->aux.possible_usages;
+ while (aux_modes) {
+ enum isl_aux_usage aux_usage = u_bit_scan(&aux_modes);
+
+ fill_surface_state(&screen->isl_dev, map, isv->res, &isv->view,
+ aux_usage);
+
+ map += SURFACE_STATE_ALIGNMENT;
+ }
} else {
fill_buffer_surface_state(&screen->isl_dev, isv->res->bo, map,
isv->view.format, tmpl->u.buf.offset,
void *map = alloc_surface_states(ice->state.surface_uploader,
- &surf->surface_state);
+ &surf->surface_state,
+ res->aux.possible_usages);
if (!unlikely(map))
return NULL;
- fill_surface_state(&screen->isl_dev, map, res, &surf->view);
+ unsigned aux_modes = res->aux.possible_usages;
+ while (aux_modes) {
+ enum isl_aux_usage aux_usage = u_bit_scan(&aux_modes);
+
+ fill_surface_state(&screen->isl_dev, map, res, &surf->view, aux_usage);
+
+ map += SURFACE_STATE_ALIGNMENT;
+ }
return psurf;
}
// XXX: these are not retained forever, use a separate uploader?
void *map =
alloc_surface_states(ice->state.surface_uploader,
- &shs->image[start_slot + i].surface_state);
+ &shs->image[start_slot + i].surface_state,
+ 1 << ISL_AUX_USAGE_NONE);
if (!unlikely(map)) {
pipe_resource_reference(&shs->image[start_slot + i].res, NULL);
return;
fill_buffer_surface_state(&screen->isl_dev, res->bo, map,
isl_fmt, 0, res->bo->size);
} else {
- fill_surface_state(&screen->isl_dev, map, res, &view);
+ /* Images don't support compression */
+ unsigned aux_modes = 1 << ISL_AUX_USAGE_NONE;
+ while (aux_modes) {
+ enum isl_aux_usage usage = u_bit_scan(&aux_modes);
+
+ fill_surface_state(&screen->isl_dev, map, res, &view, usage);
+
+ map += SURFACE_STATE_ALIGNMENT;
+ }
}
isl_surf_fill_image_param(&screen->isl_dev,
info.mocs = mocs(zres->bo);
view.format = zres->surf.format;
+
+ if (iris_resource_level_has_hiz(zres, view.base_level)) {
+ info.hiz_usage = ISL_AUX_USAGE_HIZ;
+ info.hiz_surf = &zres->aux.surf;
+ info.hiz_address = zres->aux.bo->gtt_offset;
+ }
}
if (stencil_res) {
return ice->state.null_fb.offset;
}
+static uint32_t
+surf_state_offset_for_aux(struct iris_resource *res,
+ enum isl_aux_usage aux_usage)
+{
+ return SURFACE_STATE_ALIGNMENT *
+ util_bitcount(res->aux.possible_usages & ((1 << aux_usage) - 1));
+}
+
/**
* Add a surface to the validation list, as well as the buffer containing
* the corresponding SURFACE_STATE.
static uint32_t
use_surface(struct iris_batch *batch,
struct pipe_surface *p_surf,
- bool writeable)
+ bool writeable,
+ enum isl_aux_usage aux_usage)
{
struct iris_surface *surf = (void *) p_surf;
+ struct iris_resource *res = (void *) p_surf->texture;
iris_use_pinned_bo(batch, iris_resource_bo(p_surf->texture), writeable);
iris_use_pinned_bo(batch, iris_resource_bo(surf->surface_state.res), false);
- return surf->surface_state.offset;
+ if (res->aux.bo)
+ iris_use_pinned_bo(batch, res->aux.bo, writeable);
+
+ return surf->surface_state.offset +
+ surf_state_offset_for_aux(res, aux_usage);
}
static uint32_t
-use_sampler_view(struct iris_batch *batch, struct iris_sampler_view *isv)
+use_sampler_view(struct iris_context *ice,
+ struct iris_batch *batch,
+ struct iris_sampler_view *isv)
{
+ // XXX: ASTC hacks
+ enum isl_aux_usage aux_usage =
+ iris_resource_texture_aux_usage(ice, isv->res, isv->view.format, 0);
+
iris_use_pinned_bo(batch, isv->res->bo, false);
iris_use_pinned_bo(batch, iris_resource_bo(isv->surface_state.res), false);
- return isv->surface_state.offset;
+ if (isv->res->aux.bo)
+ iris_use_pinned_bo(batch, isv->res->aux.bo, false);
+
+ return isv->surface_state.offset +
+ surf_state_offset_for_aux(isv->res, aux_usage);
}
static uint32_t
if (!shs->image[i].res)
return use_null_surface(batch, ice);
+ struct iris_resource *res = (void *) shs->image[i].res;
struct iris_state_ref *surf_state = &shs->image[i].surface_state;
+ bool write = shs->image[i].access & PIPE_IMAGE_ACCESS_WRITE;
- iris_use_pinned_bo(batch, iris_resource_bo(shs->image[i].res),
- shs->image[i].access & PIPE_IMAGE_ACCESS_WRITE);
+ iris_use_pinned_bo(batch, res->bo, write);
iris_use_pinned_bo(batch, iris_resource_bo(surf_state->res), false);
+ if (res->aux.bo)
+ iris_use_pinned_bo(batch, res->aux.bo, write);
+
return surf_state->offset;
}
/* Note that cso_fb->nr_cbufs == fs_key->nr_color_regions. */
if (cso_fb->nr_cbufs) {
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
- uint32_t addr =
- cso_fb->cbufs[i] ? use_surface(batch, cso_fb->cbufs[i], true)
- : use_null_fb_surface(batch, ice);
+ uint32_t addr;
+ if (cso_fb->cbufs[i]) {
+ addr = use_surface(batch, cso_fb->cbufs[i], true,
+ ice->state.draw_aux_usage[i]);
+ } else {
+ addr = use_null_fb_surface(batch, ice);
+ }
push_bt_entry(addr);
}
} else {
for (int i = 0; i < num_textures; i++) {
struct iris_sampler_view *view = shs->textures[i];
- uint32_t addr = view ? use_sampler_view(batch, view)
+ uint32_t addr = view ? use_sampler_view(ice, batch, view)
: use_null_surface(batch, ice);
push_bt_entry(addr);
}
iris_get_depth_stencil_resources(cso_fb->zsbuf->texture,
&zres, &sres);
if (zres) {
+ iris_cache_flush_for_depth(batch, zres->bo);
+
iris_use_pinned_bo(batch, zres->bo,
ice->state.depth_writes_enabled);
+ if (zres->aux.bo) {
+ iris_use_pinned_bo(batch, zres->aux.bo,
+ ice->state.depth_writes_enabled);
+ }
}
+
if (sres) {
+ iris_cache_flush_for_depth(batch, sres->bo);
+
iris_use_pinned_bo(batch, sres->bo,
ice->state.stencil_writes_enabled);
}
struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
const int header_dwords = GENX(BLEND_STATE_length);
- const int rt_dwords = cso_fb->nr_cbufs * GENX(BLEND_STATE_ENTRY_length);
+
+ /* Always write at least one BLEND_STATE - the final RT message will
+ * reference BLEND_STATE[0] even if there aren't color writes. There
+ * may still be alpha testing, computed depth, and so on.
+ */
+ const int rt_dwords =
+ MAX2(cso_fb->nr_cbufs, 1) * GENX(BLEND_STATE_ENTRY_length);
+
uint32_t blend_offset;
uint32_t *blend_map =
stream_state(batch, ice->state.dynamic_uploader,
if (dirty & IRIS_DIRTY_PS_BLEND) {
struct iris_blend_state *cso_blend = ice->state.cso_blend;
struct iris_depth_stencil_alpha_state *cso_zsa = ice->state.cso_zsa;
+ const struct shader_info *fs_info =
+ iris_get_shader_info(ice, MESA_SHADER_FRAGMENT);
+
uint32_t dynamic_pb[GENX(3DSTATE_PS_BLEND_length)];
iris_pack_command(GENX(3DSTATE_PS_BLEND), &dynamic_pb, pb) {
- pb.HasWriteableRT = true; // XXX: comes from somewhere :(
+ pb.HasWriteableRT = has_writeable_rt(cso_blend, fs_info);
pb.AlphaTestEnable = cso_zsa->alpha.enabled;
}
if (zres) {
iris_use_pinned_bo(batch, zres->bo,
ice->state.depth_writes_enabled);
+ if (zres->aux.bo) {
+ iris_use_pinned_bo(batch, zres->aux.bo,
+ ice->state.depth_writes_enabled);
+ }
}
if (sres) {
projects / mesa.git / blobdiff