#include "intel/common/gen_sample_positions.h"
#include "iris_batch.h"
#include "iris_context.h"
+#include "iris_defines.h"
#include "iris_pipe.h"
#include "iris_resource.h"
#include "genxml/gen_macros.h"
#include "genxml/genX_bits.h"
-#define MOCS_WB (2 << 1)
+#define MOCS_PTE (1 << 1)
+#define MOCS_WB (2 << 1)
+
+static uint32_t
+mocs(struct iris_bo *bo)
+{
+ return bo && bo->external ? MOCS_PTE : MOCS_WB;
+}
/**
* Statically assert that PIPE_* enums match the hardware packets.
#define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
static void
-_iris_emit_lrr(struct iris_batch *batch, uint32_t src, uint32_t dst)
+_iris_emit_lrr(struct iris_batch *batch, uint32_t dst, uint32_t src)
{
iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
lrr.SourceRegisterAddress = src;
* updated occasionally. See iris_binder.c for the details there.
*/
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
- #if 0
- // XXX: MOCS is stupid for this.
- sba.GeneralStateMemoryObjectControlState = MOCS_WB;
- sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
- sba.DynamicStateMemoryObjectControlState = MOCS_WB;
- sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
- sba.InstructionMemoryObjectControlState = MOCS_WB;
- sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
- #endif
+ sba.GeneralStateMOCS = MOCS_WB;
+ sba.StatelessDataPortAccessMOCS = MOCS_WB;
+ sba.DynamicStateMOCS = MOCS_WB;
+ sba.IndirectObjectMOCS = MOCS_WB;
+ sba.InstructionMOCS = MOCS_WB;
+ sba.BindlessSurfaceStateMOCS = MOCS_WB;
sba.GeneralStateBaseAddressModifyEnable = true;
sba.DynamicStateBaseAddressModifyEnable = true;
}
struct iris_vertex_buffer_state {
- /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
- uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
+ /** The VERTEX_BUFFER_STATE hardware structure. */
+ uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
/** The resource to source vertex data from. */
- struct pipe_resource *resources[33];
-
- /** The number of bound vertex buffers. */
- unsigned num_buffers;
+ struct pipe_resource *resource;
};
struct iris_depth_buffer_state {
* packets which vary by generation.
*/
struct iris_genx_state {
- struct iris_vertex_buffer_state vertex_buffers;
+ struct iris_vertex_buffer_state vertex_buffers[33];
+
+ /** The number of bound vertex buffers. */
+ uint64_t bound_vertex_buffers;
+
struct iris_depth_buffer_state depth_buffer;
uint32_t so_buffers[4 * GENX(3DSTATE_SO_BUFFER_length)];
- uint32_t streamout[4 * GENX(3DSTATE_STREAMOUT_length)];
};
/**
BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)];
bool alpha_to_coverage; /* for shader key */
+
+ /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
+ uint8_t blend_enables;
};
static enum pipe_blendfactor
struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
uint32_t *blend_entry = cso->blend_state + GENX(BLEND_STATE_length);
+ cso->blend_enables = 0;
+ STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS <= 8);
+
cso->alpha_to_coverage = state->alpha_to_coverage;
bool indep_alpha_blend = false;
src_rgb != src_alpha || dst_rgb != dst_alpha)
indep_alpha_blend = true;
+ if (rt->blend_enable)
+ cso->blend_enables |= 1u << i;
+
iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_entry, be) {
be.LogicOpEnable = state->logicop_enable;
be.LogicOpFunction = state->logicop_func;
iris_bind_blend_state(struct pipe_context *ctx, void *state)
{
struct iris_context *ice = (struct iris_context *) ctx;
- ice->state.cso_blend = state;
+ struct iris_blend_state *cso = state;
+
+ ice->state.cso_blend = cso;
+ ice->state.blend_enables = cso ? cso->blend_enables : 0;
+
ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
ice->state.dirty |= ice->state.dirty_for_nos[IRIS_NOS_BLEND];
.size_B = final_size,
.format = format,
.stride_B = cpp,
- .mocs = MOCS_WB);
+ .mocs = mocs(bo));
+}
+
+/**
+ * Allocate a SURFACE_STATE structure.
+ */
+static void *
+alloc_surface_states(struct u_upload_mgr *mgr,
+ struct iris_state_ref *ref)
+{
+ const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length);
+
+ void *map = upload_state(mgr, ref, surf_size, 64);
+
+ ref->offset += iris_bo_offset_from_base_address(iris_resource_bo(ref->res));
+
+ return map;
+}
+
+static void
+fill_surface_state(struct isl_device *isl_dev,
+ void *map,
+ struct iris_resource *res,
+ struct isl_view *view)
+{
+ struct isl_surf_fill_state_info f = {
+ .surf = &res->surf,
+ .view = view,
+ .mocs = mocs(res->bo),
+ .address = res->bo->gtt_offset,
+ };
+
+ isl_surf_fill_state_s(isl_dev, map, &f);
}
/**
pipe_reference_init(&isv->base.reference, 1);
pipe_resource_reference(&isv->base.texture, tex);
- void *map = upload_state(ice->state.surface_uploader, &isv->surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ void *map = alloc_surface_states(ice->state.surface_uploader,
+ &isv->surface_state);
if (!unlikely(map))
return NULL;
- struct iris_bo *state_bo = iris_resource_bo(isv->surface_state.res);
- isv->surface_state.offset += iris_bo_offset_from_base_address(state_bo);
-
if (util_format_is_depth_or_stencil(tmpl->format)) {
struct iris_resource *zres, *sres;
const struct util_format_description *desc =
isv->view.array_len =
tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1;
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &isv->res->surf, .view = &isv->view,
- .mocs = MOCS_WB,
- .address = isv->res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, isv->res, &isv->view);
} else {
fill_buffer_surface_state(&screen->isl_dev, isv->res->bo, map,
isv->view.format, tmpl->u.buf.offset,
return psurf;
- void *map = upload_state(ice->state.surface_uploader, &surf->surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ void *map = alloc_surface_states(ice->state.surface_uploader,
+ &surf->surface_state);
if (!unlikely(map))
return NULL;
- struct iris_bo *state_bo = iris_resource_bo(surf->surface_state.res);
- surf->surface_state.offset += iris_bo_offset_from_base_address(state_bo);
-
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &res->surf, .view = &surf->view,
- .mocs = MOCS_WB,
- .address = res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, res, &surf->view);
return psurf;
}
// XXX: these are not retained forever, use a separate uploader?
void *map =
- upload_state(ice->state.surface_uploader,
- &shs->image[start_slot + i].surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ alloc_surface_states(ice->state.surface_uploader,
+ &shs->image[start_slot + i].surface_state);
if (!unlikely(map)) {
pipe_resource_reference(&shs->image[start_slot + i].res, NULL);
return;
}
- struct iris_bo *surf_state_bo =
- iris_resource_bo(shs->image[start_slot + i].surface_state.res);
- shs->image[start_slot + i].surface_state.offset +=
- iris_bo_offset_from_base_address(surf_state_bo);
-
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
enum isl_format isl_format =
iris_format_for_usage(devinfo, img->format, usage).fmt;
.usage = usage,
};
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &res->surf, .view = &view,
- .mocs = MOCS_WB,
- .address = res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, res, &view);
} else {
fill_buffer_surface_state(&screen->isl_dev, res->bo, map,
isl_format, img->u.buf.offset,
.swizzle = ISL_SWIZZLE_IDENTITY,
};
- struct isl_depth_stencil_hiz_emit_info info = {
- .view = &view,
- .mocs = MOCS_WB,
- };
+ struct isl_depth_stencil_hiz_emit_info info = { .view = &view };
if (cso->zsbuf) {
iris_get_depth_stencil_resources(cso->zsbuf->texture, &zres,
info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset;
- info.hiz_usage = ISL_AUX_USAGE_NONE;
+ info.mocs = mocs(zres->bo);
view.format = zres->surf.format;
}
view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
info.stencil_surf = &stencil_res->surf;
info.stencil_address = stencil_res->bo->gtt_offset;
- if (!zres)
+ if (!zres) {
view.format = stencil_res->surf.format;
+ info.mocs = mocs(stencil_res->bo);
+ }
}
}
res->bo->size - cbuf->data.offset),
.format = ISL_FORMAT_R32G32B32A32_FLOAT,
.stride_B = 1,
- .mocs = MOCS_WB)
+ .mocs = mocs(res->bo))
}
/**
res->bo->size - buffer->buffer_offset),
.format = ISL_FORMAT_RAW,
.stride_B = 1,
- .mocs = MOCS_WB);
+ .mocs = mocs(res->bo));
} else {
pipe_resource_reference(&shs->ssbo[start_slot + i], NULL);
pipe_resource_reference(&shs->ssbo_surface_state[start_slot + i].res,
free(state);
}
-static void
-iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
-{
- for (unsigned i = 0; i < cso->num_buffers; i++)
- pipe_resource_reference(&cso->resources[i], NULL);
-}
-
/**
* The pipe->set_vertex_buffers() driver hook.
*
const struct pipe_vertex_buffer *buffers)
{
struct iris_context *ice = (struct iris_context *) ctx;
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
-
- iris_free_vertex_buffers(&ice->state.genx->vertex_buffers);
-
- if (!buffers)
- count = 0;
+ struct iris_genx_state *genx = ice->state.genx;
- cso->num_buffers = count;
+ ice->state.bound_vertex_buffers &= ~u_bit_consecutive64(start_slot, count);
- iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
- vb.DWordLength = 4 * MAX2(cso->num_buffers, 1) - 1;
- }
-
- uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
+ for (unsigned i = 0; i < count; i++) {
+ const struct pipe_vertex_buffer *buffer = buffers ? &buffers[i] : NULL;
+ struct iris_vertex_buffer_state *state =
+ &genx->vertex_buffers[start_slot + i];
- if (count == 0) {
- iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
- vb.VertexBufferIndex = start_slot;
- vb.NullVertexBuffer = true;
- vb.AddressModifyEnable = true;
+ if (!buffer) {
+ pipe_resource_reference(&state->resource, NULL);
+ continue;
}
- }
- for (unsigned i = 0; i < count; i++) {
- assert(!buffers[i].is_user_buffer);
+ assert(!buffer->is_user_buffer);
- pipe_resource_reference(&cso->resources[i], buffers[i].buffer.resource);
- struct iris_resource *res = (void *) cso->resources[i];
+ ice->state.bound_vertex_buffers |= 1ull << (start_slot + i);
+
+ pipe_resource_reference(&state->resource, buffer->buffer.resource);
+ struct iris_resource *res = (void *) state->resource;
if (res)
res->bind_history |= PIPE_BIND_VERTEX_BUFFER;
- iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
+ iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) {
vb.VertexBufferIndex = start_slot + i;
- vb.MOCS = MOCS_WB;
vb.AddressModifyEnable = true;
- vb.BufferPitch = buffers[i].stride;
+ vb.BufferPitch = buffer->stride;
if (res) {
vb.BufferSize = res->bo->size;
vb.BufferStartingAddress =
- ro_bo(NULL, res->bo->gtt_offset + buffers[i].buffer_offset);
+ ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
+ vb.MOCS = mocs(res->bo);
} else {
vb.NullVertexBuffer = true;
}
}
-
- vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
}
ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
}
-/**
- * Gallium CSO for stream output (transform feedback) targets.
- */
-struct iris_stream_output_target {
- struct pipe_stream_output_target base;
-
- uint32_t so_buffer[GENX(3DSTATE_SO_BUFFER_length)];
-
- /** Storage holding the offset where we're writing in the buffer */
- struct iris_state_ref offset;
-};
-
/**
* The pipe->create_stream_output_target() driver hook.
*
cso->base.buffer_size = buffer_size;
cso->base.context = ctx;
- upload_state(ctx->stream_uploader, &cso->offset, 4 * sizeof(uint32_t), 4);
-
- iris_pack_command(GENX(3DSTATE_SO_BUFFER), cso->so_buffer, sob) {
- sob.SurfaceBaseAddress =
- rw_bo(NULL, res->bo->gtt_offset + buffer_offset);
- sob.SOBufferEnable = true;
- sob.StreamOffsetWriteEnable = true;
- sob.StreamOutputBufferOffsetAddressEnable = true;
- sob.MOCS = MOCS_WB; // XXX: MOCS
-
- sob.SurfaceSize = MAX2(buffer_size / 4, 1) - 1;
-
- /* .SOBufferIndex, .StreamOffset, and .StreamOutputBufferOffsetAddress
- * are filled in later when we have stream IDs.
- */
- }
+ upload_state(ctx->stream_uploader, &cso->offset, sizeof(uint32_t), 4);
return &cso->base;
}
}
struct iris_stream_output_target *tgt = (void *) targets[i];
+ struct iris_resource *res = (void *) tgt->base.buffer;
/* Note that offsets[i] will either be 0, causing us to zero
* the value in the buffer, or 0xFFFFFFFF, which happens to mean
*/
assert(offsets[i] == 0 || offsets[i] == 0xFFFFFFFF);
- uint32_t dynamic[GENX(3DSTATE_SO_BUFFER_length)];
- iris_pack_state(GENX(3DSTATE_SO_BUFFER), dynamic, dyns) {
- dyns.SOBufferIndex = i;
- dyns.StreamOffset = offsets[i];
- dyns.StreamOutputBufferOffsetAddress =
- rw_bo(NULL, iris_resource_bo(tgt->offset.res)->gtt_offset + tgt->offset.offset + i * sizeof(uint32_t));
- }
-
- for (uint32_t j = 0; j < GENX(3DSTATE_SO_BUFFER_length); j++) {
- so_buffers[j] = tgt->so_buffer[j] | dynamic[j];
+ iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) {
+ sob.SurfaceBaseAddress =
+ rw_bo(NULL, res->bo->gtt_offset + tgt->base.buffer_offset);
+ sob.SOBufferEnable = true;
+ sob.StreamOffsetWriteEnable = true;
+ sob.StreamOutputBufferOffsetAddressEnable = true;
+ sob.MOCS = mocs(res->bo);
+
+ sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
+
+ sob.SOBufferIndex = i;
+ sob.StreamOffset = offsets[i];
+ sob.StreamOutputBufferOffsetAddress =
+ rw_bo(NULL, iris_resource_bo(tgt->offset.res)->gtt_offset +
+ tgt->offset.offset);
}
}
/* XXX: this should be generated when putting programs in place */
- // XXX: raster->sprite_coord_enable
-
for (int fs_attr = 0; fs_attr < VARYING_SLOT_MAX; fs_attr++) {
const int input_index = wm_prog_data->urb_setup[fs_attr];
if (input_index < 0 || input_index >= 16)
iris_populate_fs_key(const struct iris_context *ice,
struct brw_wm_prog_key *key)
{
- /* XXX: dirty flags? */
const struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
const struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
const struct iris_rasterizer_state *rast = ice->state.cso_rast;
key->coherent_fb_fetch = true;
- // XXX: uint64_t input_slots_valid; - for >16 inputs
-
// XXX: key->force_dual_color_blend for unigine
// XXX: respect hint for high_quality_derivatives:1;
}
pkt.Enable = true; \
\
if (prog_data->total_scratch) { \
- uint32_t scratch_addr = \
+ struct iris_bo *bo = \
iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
+ uint32_t scratch_addr = bo->gtt_offset; \
pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
}
KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
if (prog_data->total_scratch) {
- uint32_t scratch_addr =
+ struct iris_bo *bo =
iris_get_scratch_space(ice, prog_data->total_scratch,
MESA_SHADER_FRAGMENT);
+ uint32_t scratch_addr = bo->gtt_offset;
ps.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11;
ps.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr);
}
struct iris_batch *batch,
const struct pipe_draw_info *draw)
{
- // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
+ struct iris_genx_state *genx = ice->state.genx;
const uint64_t clean = ~ice->state.dirty;
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
if (clean & (IRIS_DIRTY_VS << stage)) {
struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+
if (shader) {
struct iris_bo *bo = iris_resource_bo(shader->assembly.res);
iris_use_pinned_bo(batch, bo, false);
- }
- // XXX: scratch buffer
+ struct brw_stage_prog_data *prog_data = shader->prog_data;
+
+ if (prog_data->total_scratch > 0) {
+ struct iris_bo *bo =
+ iris_get_scratch_space(ice, prog_data->total_scratch, stage);
+ iris_use_pinned_bo(batch, bo, true);
+ }
+ }
}
}
struct iris_resource *zres, *sres;
iris_get_depth_stencil_resources(cso_fb->zsbuf->texture,
&zres, &sres);
- // XXX: might not be writable...
- if (zres)
- iris_use_pinned_bo(batch, zres->bo, true);
- if (sres)
- iris_use_pinned_bo(batch, sres->bo, true);
+ if (zres) {
+ iris_use_pinned_bo(batch, zres->bo,
+ ice->state.depth_writes_enabled);
+ }
+ if (sres) {
+ iris_use_pinned_bo(batch, sres->bo,
+ ice->state.stencil_writes_enabled);
+ }
}
}
}
if (clean & IRIS_DIRTY_VERTEX_BUFFERS) {
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
- for (unsigned i = 0; i < cso->num_buffers; i++) {
- struct iris_resource *res = (void *) cso->resources[i];
- iris_use_pinned_bo(batch, res->bo, false);
+ uint64_t bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ struct pipe_resource *res = genx->vertex_buffers[i].resource;
+ iris_use_pinned_bo(batch, iris_resource_bo(res), false);
}
}
}
if (clean & IRIS_DIRTY_CS) {
struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+
if (shader) {
struct iris_bo *bo = iris_resource_bo(shader->assembly.res);
iris_use_pinned_bo(batch, bo, false);
- }
- // XXX: scratch buffer
+ struct brw_stage_prog_data *prog_data = shader->prog_data;
+
+ if (prog_data->total_scratch > 0) {
+ struct iris_bo *bo =
+ iris_get_scratch_space(ice, prog_data->total_scratch, stage);
+ iris_use_pinned_bo(batch, bo, true);
+ }
+ }
}
}
flush_for_state_base_change(batch);
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
- // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
+ sba.SurfaceStateMOCS = MOCS_WB;
sba.SurfaceStateBaseAddressModifyEnable = true;
sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
}
}
}
- /* XXX: L3 State */
-
- // XXX: this is only flagged at setup, we assume a static configuration
if (dirty & IRIS_DIRTY_URB) {
iris_upload_urb_config(ice, batch);
}
}
- /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
if (dirty & IRIS_DIRTY_WM) {
struct iris_rasterizer_state *cso = ice->state.cso_rast;
uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
struct iris_resource *zres, *sres;
iris_get_depth_stencil_resources(cso_fb->zsbuf->texture,
&zres, &sres);
- // XXX: might not be writable...
- if (zres)
- iris_use_pinned_bo(batch, zres->bo, true);
- if (sres)
- iris_use_pinned_bo(batch, sres->bo, true);
+ if (zres) {
+ iris_use_pinned_bo(batch, zres->bo,
+ ice->state.depth_writes_enabled);
+ }
+
+ if (sres) {
+ iris_use_pinned_bo(batch, sres->bo,
+ ice->state.stencil_writes_enabled);
+ }
}
}
}
if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
- const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length);
+ int count = util_bitcount64(ice->state.bound_vertex_buffers);
- if (cso->num_buffers > 0) {
+ if (count) {
/* The VF cache designers cut corners, and made the cache key's
* <VertexBufferIndex, Memory Address> tuple only consider the bottom
* 32 bits of the address. If you have two vertex buffers which get
*/
unsigned flush_flags = 0;
- for (unsigned i = 0; i < cso->num_buffers; i++) {
+ uint64_t bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
uint16_t high_bits = 0;
- struct iris_resource *res = (void *) cso->resources[i];
+ struct iris_resource *res =
+ (void *) genx->vertex_buffers[i].resource;
if (res) {
iris_use_pinned_bo(batch, res->bo, false);
if (flush_flags)
iris_emit_pipe_control_flush(batch, flush_flags);
- iris_batch_emit(batch, cso->vertex_buffers, sizeof(uint32_t) *
- (1 + vb_dwords * cso->num_buffers));
+ const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length);
+
+ uint32_t *map =
+ iris_get_command_space(batch, 4 * (1 + vb_dwords * count));
+ _iris_pack_command(batch, GENX(3DSTATE_VERTEX_BUFFERS), map, vb) {
+ vb.DWordLength = (vb_dwords * count + 1) - 2;
+ }
+ map += 1;
+
+ bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ memcpy(map, genx->vertex_buffers[i].state,
+ sizeof(uint32_t) * vb_dwords);
+ map += vb_dwords;
+ }
}
}
iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
ib.IndexFormat = draw->index_size >> 1;
- ib.MOCS = MOCS_WB;
+ ib.MOCS = mocs(bo);
ib.BufferSize = bo->size;
ib.BufferStartingAddress = ro_bo(bo, offset);
}
lri.DataDWord = 0;
}
}
+ } else if (draw->count_from_stream_output) {
+ struct iris_stream_output_target *so =
+ (void *) draw->count_from_stream_output;
+
+ // XXX: avoid if possible
+ iris_emit_pipe_control_flush(batch, PIPE_CONTROL_CS_STALL);
+
+ iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
+ lrm.RegisterAddress = CS_GPR(0);
+ lrm.MemoryAddress =
+ ro_bo(iris_resource_bo(so->offset.res), so->offset.offset);
+ }
+ iris_math_div32_gpr0(ice, batch, so->stride);
+ _iris_emit_lrr(batch, _3DPRIM_VERTEX_COUNT, CS_GPR(0));
+
+ _iris_emit_lri(batch, _3DPRIM_START_VERTEX, 0);
+ _iris_emit_lri(batch, _3DPRIM_BASE_VERTEX, 0);
+ _iris_emit_lri(batch, _3DPRIM_START_INSTANCE, 0);
+ _iris_emit_lri(batch, _3DPRIM_INSTANCE_COUNT, draw->instance_count);
}
iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
- prim.StartInstanceLocation = draw->start_instance;
- prim.InstanceCount = draw->instance_count;
- prim.VertexCountPerInstance = draw->count;
prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
prim.PredicateEnable =
ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
- // XXX: this is probably bonkers.
- prim.StartVertexLocation = draw->start;
+ if (draw->indirect || draw->count_from_stream_output) {
+ prim.IndirectParameterEnable = true;
+ } else {
+ prim.StartInstanceLocation = draw->start_instance;
+ prim.InstanceCount = draw->instance_count;
+ prim.VertexCountPerInstance = draw->count;
- prim.IndirectParameterEnable = draw->indirect != NULL;
+ // XXX: this is probably bonkers.
+ prim.StartVertexLocation = draw->start;
- if (draw->index_size) {
- prim.BaseVertexLocation += draw->index_bias;
- } else {
- prim.StartVertexLocation += draw->index_bias;
- }
+ if (draw->index_size) {
+ prim.BaseVertexLocation += draw->index_bias;
+ } else {
+ prim.StartVertexLocation += draw->index_bias;
+ }
- //prim.BaseVertexLocation = ...;
+ //prim.BaseVertexLocation = ...;
+ }
}
}
struct brw_stage_prog_data *prog_data = shader->prog_data;
struct brw_cs_prog_data *cs_prog_data = (void *) prog_data;
+ /* Always pin the binder. If we're emitting new binding table pointers,
+ * we need it. If not, we're probably inheriting old tables via the
+ * context, and need it anyway. Since true zero-bindings cases are
+ * practically non-existent, just pin it and avoid last_res tracking.
+ */
+ iris_use_pinned_bo(batch, ice->state.binder.bo, false);
+
if ((dirty & IRIS_DIRTY_CONSTANTS_CS) && shs->cbuf0_needs_upload)
upload_uniforms(ice, MESA_SHADER_COMPUTE);
iris_emit_cmd(batch, GENX(MEDIA_VFE_STATE), vfe) {
if (prog_data->total_scratch) {
- uint32_t scratch_addr =
+ struct iris_bo *bo =
iris_get_scratch_space(ice, prog_data->total_scratch,
MESA_SHADER_COMPUTE);
vfe.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11;
- vfe.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr);
+ vfe.ScratchSpaceBasePointer = rw_bo(bo, 0);
}
vfe.MaximumNumberofThreads =
static void
iris_destroy_state(struct iris_context *ice)
{
- iris_free_vertex_buffers(&ice->state.genx->vertex_buffers);
+ struct iris_genx_state *genx = ice->state.genx;
+
+ uint64_t bound_vbs = ice->state.bound_vertex_buffers;
+ while (bound_vbs) {
+ const int i = u_bit_scan64(&bound_vbs);
+ pipe_resource_reference(&genx->vertex_buffers[i].resource, NULL);
+ }
// XXX: unreference resources/surfaces.
for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
/* ------------------------------------------------------------------- */
static void
-iris_load_register_reg32(struct iris_batch *batch, uint32_t src,
- uint32_t dst)
+iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
+ uint32_t src)
{
- _iris_emit_lrr(batch, src, dst);
+ _iris_emit_lrr(batch, dst, src);
}
static void
-iris_load_register_reg64(struct iris_batch *batch, uint32_t src,
- uint32_t dst)
+iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
+ uint32_t src)
{
- _iris_emit_lrr(batch, src, dst);
- _iris_emit_lrr(batch, src + 4, dst + 4);
+ _iris_emit_lrr(batch, dst, src);
+ _iris_emit_lrr(batch, dst + 4, src + 4);
}
static void
projects / mesa.git / blobdiff