#include "intel/common/gen_sample_positions.h"
#include "iris_batch.h"
#include "iris_context.h"
+#include "iris_defines.h"
#include "iris_pipe.h"
#include "iris_resource.h"
#include "genxml/gen_macros.h"
#include "genxml/genX_bits.h"
-#define MOCS_WB (2 << 1)
+#define MOCS_PTE (1 << 1)
+#define MOCS_WB (2 << 1)
+
+static uint32_t
+mocs(struct iris_bo *bo)
+{
+ return bo && bo->external ? MOCS_PTE : MOCS_WB;
+}
/**
* Statically assert that PIPE_* enums match the hardware packets.
}
#define iris_emit_lri(b, r, v) _iris_emit_lri(b, GENX(r##_num), v)
+static void
+_iris_emit_lrr(struct iris_batch *batch, uint32_t dst, uint32_t src)
+{
+ iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_REG), lrr) {
+ lrr.SourceRegisterAddress = src;
+ lrr.DestinationRegisterAddress = dst;
+ }
+}
+
static void
emit_pipeline_select(struct iris_batch *batch, uint32_t pipeline)
{
* updated occasionally. See iris_binder.c for the details there.
*/
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
- #if 0
- // XXX: MOCS is stupid for this.
- sba.GeneralStateMemoryObjectControlState = MOCS_WB;
- sba.StatelessDataPortAccessMemoryObjectControlState = MOCS_WB;
- sba.DynamicStateMemoryObjectControlState = MOCS_WB;
- sba.IndirectObjectMemoryObjectControlState = MOCS_WB;
- sba.InstructionMemoryObjectControlState = MOCS_WB;
- sba.BindlessSurfaceStateMemoryObjectControlState = MOCS_WB;
- #endif
+ sba.GeneralStateMOCS = MOCS_WB;
+ sba.StatelessDataPortAccessMOCS = MOCS_WB;
+ sba.DynamicStateMOCS = MOCS_WB;
+ sba.IndirectObjectMOCS = MOCS_WB;
+ sba.InstructionMOCS = MOCS_WB;
+ sba.BindlessSurfaceStateMOCS = MOCS_WB;
sba.GeneralStateBaseAddressModifyEnable = true;
sba.DynamicStateBaseAddressModifyEnable = true;
emit_pipeline_select(batch, GPGPU);
+ const bool has_slm = true;
+ const bool wants_dc_cache = true;
+
+ const struct gen_l3_weights w =
+ gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
+ const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
+
+ uint32_t reg_val;
+ iris_pack_state(GENX(L3CNTLREG), ®_val, reg) {
+ reg.SLMEnable = has_slm;
+#if GEN_GEN == 11
+ /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
+ * in L3CNTLREG register. The default setting of the bit is not the
+ * desirable behavior.
+ */
+ reg.ErrorDetectionBehaviorControl = true;
+#endif
+ reg.URBAllocation = cfg->n[GEN_L3P_URB];
+ reg.ROAllocation = cfg->n[GEN_L3P_RO];
+ reg.DCAllocation = cfg->n[GEN_L3P_DC];
+ reg.AllAllocation = cfg->n[GEN_L3P_ALL];
+ }
+ iris_emit_lri(batch, L3CNTLREG, reg_val);
+
init_state_base_address(batch);
#if GEN_GEN == 9
}
struct iris_vertex_buffer_state {
- /** The 3DSTATE_VERTEX_BUFFERS hardware packet. */
- uint32_t vertex_buffers[1 + 33 * GENX(VERTEX_BUFFER_STATE_length)];
+ /** The VERTEX_BUFFER_STATE hardware structure. */
+ uint32_t state[GENX(VERTEX_BUFFER_STATE_length)];
/** The resource to source vertex data from. */
- struct pipe_resource *resources[33];
-
- /** The number of bound vertex buffers. */
- unsigned num_buffers;
+ struct pipe_resource *resource;
};
struct iris_depth_buffer_state {
* packets which vary by generation.
*/
struct iris_genx_state {
- /** SF_CLIP_VIEWPORT */
- uint32_t sf_cl_vp[GENX(SF_CLIP_VIEWPORT_length) * IRIS_MAX_VIEWPORTS];
+ struct iris_vertex_buffer_state vertex_buffers[33];
+
+ /** The number of bound vertex buffers. */
+ uint64_t bound_vertex_buffers;
- struct iris_vertex_buffer_state vertex_buffers;
struct iris_depth_buffer_state depth_buffer;
uint32_t so_buffers[4 * GENX(3DSTATE_SO_BUFFER_length)];
- uint32_t streamout[4 * GENX(3DSTATE_STREAMOUT_length)];
};
/**
BRW_MAX_DRAW_BUFFERS * GENX(BLEND_STATE_ENTRY_length)];
bool alpha_to_coverage; /* for shader key */
+
+ /** Bitfield of whether blending is enabled for RT[i] - for aux resolves */
+ uint8_t blend_enables;
};
+static enum pipe_blendfactor
+fix_blendfactor(enum pipe_blendfactor f, bool alpha_to_one)
+{
+ if (alpha_to_one) {
+ if (f == PIPE_BLENDFACTOR_SRC1_ALPHA)
+ return PIPE_BLENDFACTOR_ONE;
+
+ if (f == PIPE_BLENDFACTOR_INV_SRC1_ALPHA)
+ return PIPE_BLENDFACTOR_ZERO;
+ }
+
+ return f;
+}
+
/**
* The pipe->create_blend_state() driver hook.
*
const struct pipe_blend_state *state)
{
struct iris_blend_state *cso = malloc(sizeof(struct iris_blend_state));
- uint32_t *blend_state = cso->blend_state;
+ uint32_t *blend_entry = cso->blend_state + GENX(BLEND_STATE_length);
+
+ cso->blend_enables = 0;
+ STATIC_ASSERT(BRW_MAX_DRAW_BUFFERS <= 8);
cso->alpha_to_coverage = state->alpha_to_coverage;
- iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
- /* pb.HasWriteableRT is filled in at draw time. */
- /* pb.AlphaTestEnable is filled in at draw time. */
- pb.AlphaToCoverageEnable = state->alpha_to_coverage;
- pb.IndependentAlphaBlendEnable = state->independent_blend_enable;
+ bool indep_alpha_blend = false;
- pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
+ for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
+ const struct pipe_rt_blend_state *rt =
+ &state->rt[state->independent_blend_enable ? i : 0];
- pb.SourceBlendFactor = state->rt[0].rgb_src_factor;
- pb.SourceAlphaBlendFactor = state->rt[0].alpha_func;
- pb.DestinationBlendFactor = state->rt[0].rgb_dst_factor;
- pb.DestinationAlphaBlendFactor = state->rt[0].alpha_dst_factor;
- }
+ enum pipe_blendfactor src_rgb =
+ fix_blendfactor(rt->rgb_src_factor, state->alpha_to_one);
+ enum pipe_blendfactor src_alpha =
+ fix_blendfactor(rt->alpha_src_factor, state->alpha_to_one);
+ enum pipe_blendfactor dst_rgb =
+ fix_blendfactor(rt->rgb_dst_factor, state->alpha_to_one);
+ enum pipe_blendfactor dst_alpha =
+ fix_blendfactor(rt->alpha_dst_factor, state->alpha_to_one);
- iris_pack_state(GENX(BLEND_STATE), blend_state, bs) {
- bs.AlphaToCoverageEnable = state->alpha_to_coverage;
- bs.IndependentAlphaBlendEnable = state->independent_blend_enable;
- bs.AlphaToOneEnable = state->alpha_to_one;
- bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
- bs.ColorDitherEnable = state->dither;
- /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
- }
+ if (rt->rgb_func != rt->alpha_func ||
+ src_rgb != src_alpha || dst_rgb != dst_alpha)
+ indep_alpha_blend = true;
- blend_state += GENX(BLEND_STATE_length);
+ if (rt->blend_enable)
+ cso->blend_enables |= 1u << i;
- for (int i = 0; i < BRW_MAX_DRAW_BUFFERS; i++) {
- const struct pipe_rt_blend_state *rt =
- &state->rt[state->independent_blend_enable ? i : 0];
- iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_state, be) {
+ iris_pack_state(GENX(BLEND_STATE_ENTRY), blend_entry, be) {
be.LogicOpEnable = state->logicop_enable;
be.LogicOpFunction = state->logicop_func;
be.ColorBlendFunction = rt->rgb_func;
be.AlphaBlendFunction = rt->alpha_func;
- be.SourceBlendFactor = rt->rgb_src_factor;
- be.SourceAlphaBlendFactor = rt->alpha_func;
- be.DestinationBlendFactor = rt->rgb_dst_factor;
- be.DestinationAlphaBlendFactor = rt->alpha_dst_factor;
+ be.SourceBlendFactor = src_rgb;
+ be.SourceAlphaBlendFactor = src_alpha;
+ be.DestinationBlendFactor = dst_rgb;
+ be.DestinationAlphaBlendFactor = dst_alpha;
be.WriteDisableRed = !(rt->colormask & PIPE_MASK_R);
be.WriteDisableGreen = !(rt->colormask & PIPE_MASK_G);
be.WriteDisableBlue = !(rt->colormask & PIPE_MASK_B);
be.WriteDisableAlpha = !(rt->colormask & PIPE_MASK_A);
}
- blend_state += GENX(BLEND_STATE_ENTRY_length);
+ blend_entry += GENX(BLEND_STATE_ENTRY_length);
+ }
+
+ iris_pack_command(GENX(3DSTATE_PS_BLEND), cso->ps_blend, pb) {
+ /* pb.HasWriteableRT is filled in at draw time. */
+ /* pb.AlphaTestEnable is filled in at draw time. */
+ pb.AlphaToCoverageEnable = state->alpha_to_coverage;
+ pb.IndependentAlphaBlendEnable = indep_alpha_blend;
+
+ pb.ColorBufferBlendEnable = state->rt[0].blend_enable;
+
+ pb.SourceBlendFactor =
+ fix_blendfactor(state->rt[0].rgb_src_factor, state->alpha_to_one);
+ pb.SourceAlphaBlendFactor =
+ fix_blendfactor(state->rt[0].alpha_src_factor, state->alpha_to_one);
+ pb.DestinationBlendFactor =
+ fix_blendfactor(state->rt[0].rgb_dst_factor, state->alpha_to_one);
+ pb.DestinationAlphaBlendFactor =
+ fix_blendfactor(state->rt[0].alpha_dst_factor, state->alpha_to_one);
+ }
+
+ iris_pack_state(GENX(BLEND_STATE), cso->blend_state, bs) {
+ bs.AlphaToCoverageEnable = state->alpha_to_coverage;
+ bs.IndependentAlphaBlendEnable = indep_alpha_blend;
+ bs.AlphaToOneEnable = state->alpha_to_one;
+ bs.AlphaToCoverageDitherEnable = state->alpha_to_coverage;
+ bs.ColorDitherEnable = state->dither;
+ /* bl.AlphaTestEnable and bs.AlphaTestFunction are filled in later. */
}
+
return cso;
}
iris_bind_blend_state(struct pipe_context *ctx, void *state)
{
struct iris_context *ice = (struct iris_context *) ctx;
- ice->state.cso_blend = state;
+ struct iris_blend_state *cso = state;
+
+ ice->state.cso_blend = cso;
+ ice->state.blend_enables = cso ? cso->blend_enables : 0;
+
ice->state.dirty |= IRIS_DIRTY_PS_BLEND;
ice->state.dirty |= IRIS_DIRTY_BLEND_STATE;
ice->state.dirty |= ice->state.dirty_for_nos[IRIS_NOS_BLEND];
bool flatshade_first; /* for stream output */
bool clamp_fragment_color; /* for shader state */
bool light_twoside; /* for shader state */
- bool rasterizer_discard; /* for 3DSTATE_STREAMOUT */
+ bool rasterizer_discard; /* for 3DSTATE_STREAMOUT and 3DSTATE_CLIP */
bool half_pixel_center; /* for 3DSTATE_MULTISAMPLE */
bool line_stipple_enable;
bool poly_stipple_enable;
not necessary?
{
poly_smooth
- force_persample_interp - ?
bottom_edge_rule
offset_units_unscaled - cap not exposed
/* cl.NonPerspectiveBarycentricEnable is filled in at draw time from
* the FS program; cl.ForceZeroRTAIndexEnable is filled in from the FB.
*/
- cl.StatisticsEnable = true;
cl.EarlyCullEnable = true;
cl.UserClipDistanceClipTestEnableBitmask = state->clip_plane_enable;
cl.ForceUserClipDistanceClipTestEnableBitmask = true;
cl.APIMode = state->clip_halfz ? APIMODE_D3D : APIMODE_OGL;
cl.GuardbandClipTestEnable = true;
- cl.ClipMode = CLIPMODE_NORMAL;
cl.ClipEnable = true;
cl.ViewportXYClipTestEnable = state->point_tri_clip;
cl.MinimumPointWidth = 0.125;
if (cso_changed(line_stipple_enable) || cso_changed(poly_stipple_enable))
ice->state.dirty |= IRIS_DIRTY_WM;
- if (cso_changed(rasterizer_discard) || cso_changed(flatshade_first))
+ if (cso_changed(rasterizer_discard))
+ ice->state.dirty |= IRIS_DIRTY_STREAMOUT | IRIS_DIRTY_CLIP;
+
+ if (cso_changed(flatshade_first))
ice->state.dirty |= IRIS_DIRTY_STREAMOUT;
if (cso_changed(depth_clip_near) || cso_changed(depth_clip_far) ||
cso_changed(clip_halfz))
ice->state.dirty |= IRIS_DIRTY_CC_VIEWPORT;
- if (cso_changed(sprite_coord_enable) || cso_changed(light_twoside))
+ if (cso_changed(sprite_coord_enable) ||
+ cso_changed(sprite_coord_mode) ||
+ cso_changed(light_twoside))
ice->state.dirty |= IRIS_DIRTY_SBE;
}
struct iris_shader_state *shs = &ice->state.shaders[stage];
assert(start + count <= IRIS_MAX_TEXTURE_SAMPLERS);
- shs->num_samplers = MAX2(shs->num_samplers, start + count);
for (int i = 0; i < count; i++) {
shs->samplers[start + i] = states[i];
.size_B = final_size,
.format = format,
.stride_B = cpp,
- .mocs = MOCS_WB);
+ .mocs = mocs(bo));
+}
+
+/**
+ * Allocate a SURFACE_STATE structure.
+ */
+static void *
+alloc_surface_states(struct u_upload_mgr *mgr,
+ struct iris_state_ref *ref)
+{
+ const unsigned surf_size = 4 * GENX(RENDER_SURFACE_STATE_length);
+
+ void *map = upload_state(mgr, ref, surf_size, 64);
+
+ ref->offset += iris_bo_offset_from_base_address(iris_resource_bo(ref->res));
+
+ return map;
+}
+
+static void
+fill_surface_state(struct isl_device *isl_dev,
+ void *map,
+ struct iris_resource *res,
+ struct isl_view *view)
+{
+ struct isl_surf_fill_state_info f = {
+ .surf = &res->surf,
+ .view = view,
+ .mocs = mocs(res->bo),
+ .address = res->bo->gtt_offset,
+ };
+
+ isl_surf_fill_state_s(isl_dev, map, &f);
}
/**
pipe_reference_init(&isv->base.reference, 1);
pipe_resource_reference(&isv->base.texture, tex);
- void *map = upload_state(ice->state.surface_uploader, &isv->surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ void *map = alloc_surface_states(ice->state.surface_uploader,
+ &isv->surface_state);
if (!unlikely(map))
return NULL;
- struct iris_bo *state_bo = iris_resource_bo(isv->surface_state.res);
- isv->surface_state.offset += iris_bo_offset_from_base_address(state_bo);
-
if (util_format_is_depth_or_stencil(tmpl->format)) {
struct iris_resource *zres, *sres;
const struct util_format_description *desc =
isv->res = (struct iris_resource *) tex;
- isl_surf_usage_flags_t usage =
- ISL_SURF_USAGE_TEXTURE_BIT |
- (isv->res->surf.usage & ISL_SURF_USAGE_CUBE_BIT);
+ isl_surf_usage_flags_t usage = ISL_SURF_USAGE_TEXTURE_BIT;
+
+ if (isv->base.target == PIPE_TEXTURE_CUBE ||
+ isv->base.target == PIPE_TEXTURE_CUBE_ARRAY)
+ usage |= ISL_SURF_USAGE_CUBE_BIT;
const struct iris_format_info fmt =
iris_format_for_usage(devinfo, tmpl->format, usage);
if (tmpl->target != PIPE_BUFFER) {
isv->view.base_level = tmpl->u.tex.first_level;
isv->view.levels = tmpl->u.tex.last_level - tmpl->u.tex.first_level + 1;
+ // XXX: do I need to port f9fd0cf4790cb2a530e75d1a2206dbb9d8af7cb2?
isv->view.base_array_layer = tmpl->u.tex.first_layer;
isv->view.array_len =
tmpl->u.tex.last_layer - tmpl->u.tex.first_layer + 1;
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &isv->res->surf, .view = &isv->view,
- .mocs = MOCS_WB,
- .address = isv->res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, isv->res, &isv->view);
} else {
fill_buffer_surface_state(&screen->isl_dev, isv->res->bo, map,
isv->view.format, tmpl->u.buf.offset,
return psurf;
- void *map = upload_state(ice->state.surface_uploader, &surf->surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ void *map = alloc_surface_states(ice->state.surface_uploader,
+ &surf->surface_state);
if (!unlikely(map))
return NULL;
- struct iris_bo *state_bo = iris_resource_bo(surf->surface_state.res);
- surf->surface_state.offset += iris_bo_offset_from_base_address(state_bo);
-
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &res->surf, .view = &surf->view,
- .mocs = MOCS_WB,
- .address = res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, res, &surf->view);
return psurf;
}
gl_shader_stage stage = stage_from_pipe(p_stage);
struct iris_shader_state *shs = &ice->state.shaders[stage];
+ shs->bound_image_views &= ~u_bit_consecutive(start_slot, count);
+
for (unsigned i = 0; i < count; i++) {
if (p_images && p_images[i].resource) {
const struct pipe_image_view *img = &p_images[i];
struct iris_resource *res = (void *) img->resource;
pipe_resource_reference(&shs->image[start_slot + i].res, &res->base);
+ shs->bound_image_views |= 1 << (start_slot + i);
+
+ res->bind_history |= PIPE_BIND_SHADER_IMAGE;
+
// XXX: these are not retained forever, use a separate uploader?
void *map =
- upload_state(ice->state.surface_uploader,
- &shs->image[start_slot + i].surface_state,
- 4 * GENX(RENDER_SURFACE_STATE_length), 64);
+ alloc_surface_states(ice->state.surface_uploader,
+ &shs->image[start_slot + i].surface_state);
if (!unlikely(map)) {
pipe_resource_reference(&shs->image[start_slot + i].res, NULL);
return;
}
- struct iris_bo *surf_state_bo =
- iris_resource_bo(shs->image[start_slot + i].surface_state.res);
- shs->image[start_slot + i].surface_state.offset +=
- iris_bo_offset_from_base_address(surf_state_bo);
-
isl_surf_usage_flags_t usage = ISL_SURF_USAGE_STORAGE_BIT;
enum isl_format isl_format =
iris_format_for_usage(devinfo, img->format, usage).fmt;
.usage = usage,
};
- isl_surf_fill_state(&screen->isl_dev, map,
- .surf = &res->surf, .view = &view,
- .mocs = MOCS_WB,
- .address = res->bo->gtt_offset);
- // .aux_surf =
- // .clear_color = clear_color,
+ fill_surface_state(&screen->isl_dev, map, res, &view);
} else {
fill_buffer_surface_state(&screen->isl_dev, res->bo, map,
isl_format, img->u.buf.offset,
gl_shader_stage stage = stage_from_pipe(p_stage);
struct iris_shader_state *shs = &ice->state.shaders[stage];
- unsigned i;
- for (i = 0; i < count; i++) {
- pipe_sampler_view_reference((struct pipe_sampler_view **)
- &shs->textures[i], views[i]);
- }
- for (; i < shs->num_textures; i++) {
+ shs->bound_sampler_views &= ~u_bit_consecutive(start, count);
+
+ for (unsigned i = 0; i < count; i++) {
pipe_sampler_view_reference((struct pipe_sampler_view **)
- &shs->textures[i], NULL);
+ &shs->textures[start + i], views[i]);
+ struct iris_sampler_view *view = (void *) views[i];
+ if (view) {
+ view->res->bind_history |= PIPE_BIND_SAMPLER_VIEW;
+ shs->bound_sampler_views |= 1 << (start + i);
+ }
}
- shs->num_textures = count;
-
ice->state.dirty |= (IRIS_DIRTY_BINDINGS_VS << stage);
}
return copysignf(state->scale[axis], sign) + state->translate[axis];
}
-#if 0
static void
calculate_guardband_size(uint32_t fb_width, uint32_t fb_height,
float m00, float m11, float m30, float m31,
*ymax = 0.0f;
}
}
-#endif
/**
* The pipe->set_viewport_states() driver hook.
const struct pipe_viewport_state *states)
{
struct iris_context *ice = (struct iris_context *) ctx;
- struct iris_genx_state *genx = ice->state.genx;
- uint32_t *vp_map =
- &genx->sf_cl_vp[start_slot * GENX(SF_CLIP_VIEWPORT_length)];
-
- for (unsigned i = 0; i < count; i++) {
- const struct pipe_viewport_state *state = &states[i];
-
- memcpy(&ice->state.viewports[start_slot + i], state, sizeof(*state));
-
- iris_pack_state(GENX(SF_CLIP_VIEWPORT), vp_map, vp) {
- vp.ViewportMatrixElementm00 = state->scale[0];
- vp.ViewportMatrixElementm11 = state->scale[1];
- vp.ViewportMatrixElementm22 = state->scale[2];
- vp.ViewportMatrixElementm30 = state->translate[0];
- vp.ViewportMatrixElementm31 = state->translate[1];
- vp.ViewportMatrixElementm32 = state->translate[2];
- /* XXX: in i965 this is computed based on the drawbuffer size,
- * but we don't have that here...
- */
- vp.XMinClipGuardband = -1.0;
- vp.XMaxClipGuardband = 1.0;
- vp.YMinClipGuardband = -1.0;
- vp.YMaxClipGuardband = 1.0;
- vp.XMinViewPort = viewport_extent(state, 0, -1.0f);
- vp.XMaxViewPort = viewport_extent(state, 0, 1.0f) - 1;
- vp.YMinViewPort = viewport_extent(state, 1, -1.0f);
- vp.YMaxViewPort = viewport_extent(state, 1, 1.0f) - 1;
- }
- vp_map += GENX(SF_CLIP_VIEWPORT_length);
- }
+ memcpy(&ice->state.viewports[start_slot], states, sizeof(*states) * count);
ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
ice->state.dirty |= IRIS_DIRTY_CLIP;
}
+ if (cso->width != state->width || cso->height != state->height) {
+ ice->state.dirty |= IRIS_DIRTY_SF_CL_VIEWPORT;
+ }
+
util_copy_framebuffer_state(cso, state);
cso->samples = samples;
.swizzle = ISL_SWIZZLE_IDENTITY,
};
- struct isl_depth_stencil_hiz_emit_info info = {
- .view = &view,
- .mocs = MOCS_WB,
- };
+ struct isl_depth_stencil_hiz_emit_info info = { .view = &view };
if (cso->zsbuf) {
iris_get_depth_stencil_resources(cso->zsbuf->texture, &zres,
info.depth_surf = &zres->surf;
info.depth_address = zres->bo->gtt_offset;
- info.hiz_usage = ISL_AUX_USAGE_NONE;
+ info.mocs = mocs(zres->bo);
view.format = zres->surf.format;
}
view.usage |= ISL_SURF_USAGE_STENCIL_BIT;
info.stencil_surf = &stencil_res->surf;
info.stencil_address = stencil_res->bo->gtt_offset;
- if (!zres)
+ if (!zres) {
view.format = stencil_res->surf.format;
+ info.mocs = mocs(stencil_res->bo);
+ }
}
}
* be set in this packet."
*/
// XXX: does this need to happen at 3DSTATE_BTP_PS time?
- iris_emit_pipe_control_flush(&ice->render_batch,
+ iris_emit_pipe_control_flush(&ice->batches[IRIS_BATCH_RENDER],
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_STALL_AT_SCOREBOARD);
#endif
res->bo->size - cbuf->data.offset),
.format = ISL_FORMAT_R32G32B32A32_FLOAT,
.stride_B = 1,
- .mocs = MOCS_WB)
+ .mocs = mocs(res->bo))
}
/**
pipe_resource_reference(&cbuf->data.res, input->buffer);
cbuf->data.offset = input->buffer_offset;
+ struct iris_resource *res = (void *) cbuf->data.res;
+ res->bind_history |= PIPE_BIND_CONSTANT_BUFFER;
+
upload_ubo_surf_state(ice, cbuf, input->buffer_size);
} else {
pipe_resource_reference(&cbuf->data.res, NULL);
int plane = BRW_PARAM_BUILTIN_CLIP_PLANE_IDX(sysval);
int comp = BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(sysval);
value = fui(ice->state.clip_planes.ucp[plane][comp]);
+ } else if (sysval == BRW_PARAM_BUILTIN_PATCH_VERTICES_IN) {
+ if (stage == MESA_SHADER_TESS_CTRL) {
+ value = ice->state.vertices_per_patch;
+ } else {
+ assert(stage == MESA_SHADER_TESS_EVAL);
+ const struct shader_info *tcs_info =
+ iris_get_shader_info(ice, MESA_SHADER_TESS_CTRL);
+ assert(tcs_info);
+
+ value = tcs_info->tess.tcs_vertices_out;
+ }
} else {
assert(!"unhandled system value");
}
struct iris_resource *res = (void *) buffer->buffer;
pipe_resource_reference(&shs->ssbo[start_slot + i], &res->base);
+ res->bind_history |= PIPE_BIND_SHADER_BUFFER;
+
// XXX: these are not retained forever, use a separate uploader?
void *map =
upload_state(ice->state.surface_uploader,
res->bo->size - buffer->buffer_offset),
.format = ISL_FORMAT_RAW,
.stride_B = 1,
- .mocs = MOCS_WB);
+ .mocs = mocs(res->bo));
} else {
pipe_resource_reference(&shs->ssbo[start_slot + i], NULL);
pipe_resource_reference(&shs->ssbo_surface_state[start_slot + i].res,
free(state);
}
-static void
-iris_free_vertex_buffers(struct iris_vertex_buffer_state *cso)
-{
- for (unsigned i = 0; i < cso->num_buffers; i++)
- pipe_resource_reference(&cso->resources[i], NULL);
-}
-
/**
* The pipe->set_vertex_buffers() driver hook.
*
const struct pipe_vertex_buffer *buffers)
{
struct iris_context *ice = (struct iris_context *) ctx;
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
-
- iris_free_vertex_buffers(&ice->state.genx->vertex_buffers);
+ struct iris_genx_state *genx = ice->state.genx;
- if (!buffers)
- count = 0;
+ ice->state.bound_vertex_buffers &= ~u_bit_consecutive64(start_slot, count);
- cso->num_buffers = count;
+ for (unsigned i = 0; i < count; i++) {
+ const struct pipe_vertex_buffer *buffer = buffers ? &buffers[i] : NULL;
+ struct iris_vertex_buffer_state *state =
+ &genx->vertex_buffers[start_slot + i];
- iris_pack_command(GENX(3DSTATE_VERTEX_BUFFERS), cso->vertex_buffers, vb) {
- vb.DWordLength = 4 * MAX2(cso->num_buffers, 1) - 1;
- }
+ if (!buffer) {
+ pipe_resource_reference(&state->resource, NULL);
+ continue;
+ }
- uint32_t *vb_pack_dest = &cso->vertex_buffers[1];
+ assert(!buffer->is_user_buffer);
- if (count == 0) {
- iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
- vb.VertexBufferIndex = start_slot;
- vb.NullVertexBuffer = true;
- vb.AddressModifyEnable = true;
- }
- }
+ ice->state.bound_vertex_buffers |= 1ull << (start_slot + i);
- for (unsigned i = 0; i < count; i++) {
- assert(!buffers[i].is_user_buffer);
+ pipe_resource_reference(&state->resource, buffer->buffer.resource);
+ struct iris_resource *res = (void *) state->resource;
- pipe_resource_reference(&cso->resources[i], buffers[i].buffer.resource);
- struct iris_resource *res = (void *) cso->resources[i];
+ if (res)
+ res->bind_history |= PIPE_BIND_VERTEX_BUFFER;
- iris_pack_state(GENX(VERTEX_BUFFER_STATE), vb_pack_dest, vb) {
+ iris_pack_state(GENX(VERTEX_BUFFER_STATE), state->state, vb) {
vb.VertexBufferIndex = start_slot + i;
- vb.MOCS = MOCS_WB;
vb.AddressModifyEnable = true;
- vb.BufferPitch = buffers[i].stride;
+ vb.BufferPitch = buffer->stride;
if (res) {
vb.BufferSize = res->bo->size;
vb.BufferStartingAddress =
- ro_bo(NULL, res->bo->gtt_offset + buffers[i].buffer_offset);
+ ro_bo(NULL, res->bo->gtt_offset + (int) buffer->buffer_offset);
+ vb.MOCS = mocs(res->bo);
} else {
vb.NullVertexBuffer = true;
}
}
-
- vb_pack_dest += GENX(VERTEX_BUFFER_STATE_length);
}
ice->state.dirty |= IRIS_DIRTY_VERTEX_BUFFERS;
ice->state.dirty |= IRIS_DIRTY_VERTEX_ELEMENTS;
}
-/**
- * Gallium CSO for stream output (transform feedback) targets.
- */
-struct iris_stream_output_target {
- struct pipe_stream_output_target base;
-
- uint32_t so_buffer[GENX(3DSTATE_SO_BUFFER_length)];
-
- /** Storage holding the offset where we're writing in the buffer */
- struct iris_state_ref offset;
-};
-
/**
* The pipe->create_stream_output_target() driver hook.
*
*/
static struct pipe_stream_output_target *
iris_create_stream_output_target(struct pipe_context *ctx,
- struct pipe_resource *res,
+ struct pipe_resource *p_res,
unsigned buffer_offset,
unsigned buffer_size)
{
+ struct iris_resource *res = (void *) p_res;
struct iris_stream_output_target *cso = calloc(1, sizeof(*cso));
if (!cso)
return NULL;
+ res->bind_history |= PIPE_BIND_STREAM_OUTPUT;
+
pipe_reference_init(&cso->base.reference, 1);
- pipe_resource_reference(&cso->base.buffer, res);
+ pipe_resource_reference(&cso->base.buffer, p_res);
cso->base.buffer_offset = buffer_offset;
cso->base.buffer_size = buffer_size;
cso->base.context = ctx;
- upload_state(ctx->stream_uploader, &cso->offset, 4 * sizeof(uint32_t), 4);
-
- iris_pack_command(GENX(3DSTATE_SO_BUFFER), cso->so_buffer, sob) {
- sob.SurfaceBaseAddress =
- rw_bo(NULL, iris_resource_bo(res)->gtt_offset + buffer_offset);
- sob.SOBufferEnable = true;
- sob.StreamOffsetWriteEnable = true;
- sob.StreamOutputBufferOffsetAddressEnable = true;
- sob.MOCS = MOCS_WB; // XXX: MOCS
-
- sob.SurfaceSize = MAX2(buffer_size / 4, 1) - 1;
-
- /* .SOBufferIndex, .StreamOffset, and .StreamOutputBufferOffsetAddress
- * are filled in later when we have stream IDs.
- */
- }
+ upload_state(ctx->stream_uploader, &cso->offset, sizeof(uint32_t), 4);
return &cso->base;
}
}
struct iris_stream_output_target *tgt = (void *) targets[i];
+ struct iris_resource *res = (void *) tgt->base.buffer;
/* Note that offsets[i] will either be 0, causing us to zero
* the value in the buffer, or 0xFFFFFFFF, which happens to mean
*/
assert(offsets[i] == 0 || offsets[i] == 0xFFFFFFFF);
- uint32_t dynamic[GENX(3DSTATE_SO_BUFFER_length)];
- iris_pack_state(GENX(3DSTATE_SO_BUFFER), dynamic, dyns) {
- dyns.SOBufferIndex = i;
- dyns.StreamOffset = offsets[i];
- dyns.StreamOutputBufferOffsetAddress =
- rw_bo(NULL, iris_resource_bo(tgt->offset.res)->gtt_offset + tgt->offset.offset + i * sizeof(uint32_t));
- }
-
- for (uint32_t j = 0; j < GENX(3DSTATE_SO_BUFFER_length); j++) {
- so_buffers[j] = tgt->so_buffer[j] | dynamic[j];
+ iris_pack_command(GENX(3DSTATE_SO_BUFFER), so_buffers, sob) {
+ sob.SurfaceBaseAddress =
+ rw_bo(NULL, res->bo->gtt_offset + tgt->base.buffer_offset);
+ sob.SOBufferEnable = true;
+ sob.StreamOffsetWriteEnable = true;
+ sob.StreamOutputBufferOffsetAddressEnable = true;
+ sob.MOCS = mocs(res->bo);
+
+ sob.SurfaceSize = MAX2(tgt->base.buffer_size / 4, 1) - 1;
+
+ sob.SOBufferIndex = i;
+ sob.StreamOffset = offsets[i];
+ sob.StreamOutputBufferOffsetAddress =
+ rw_bo(NULL, iris_resource_bo(tgt->offset.res)->gtt_offset +
+ tgt->offset.offset);
}
}
/* XXX: this should be generated when putting programs in place */
- // XXX: raster->sprite_coord_enable
-
for (int fs_attr = 0; fs_attr < VARYING_SLOT_MAX; fs_attr++) {
const int input_index = wm_prog_data->urb_setup[fs_attr];
if (input_index < 0 || input_index >= 16)
/* ------------------------------------------------------------------- */
-/**
- * Set sampler-related program key fields based on the current state.
- */
-static void
-iris_populate_sampler_key(const struct iris_context *ice,
- struct brw_sampler_prog_key_data *key)
-{
- for (int i = 0; i < MAX_SAMPLERS; i++) {
- key->swizzles[i] = 0x688; /* XYZW */
- }
-}
-
/**
* Populate VS program key fields based on the current state.
*/
{
const struct iris_rasterizer_state *cso_rast = ice->state.cso_rast;
- iris_populate_sampler_key(ice, &key->tex);
-
if (info->clip_distance_array_size == 0 &&
(info->outputs_written & (VARYING_BIT_POS | VARYING_BIT_CLIP_VERTEX)))
key->nr_userclip_plane_consts = cso_rast->num_clip_plane_consts;
iris_populate_tcs_key(const struct iris_context *ice,
struct brw_tcs_prog_key *key)
{
- iris_populate_sampler_key(ice, &key->tex);
}
/**
iris_populate_tes_key(const struct iris_context *ice,
struct brw_tes_prog_key *key)
{
- iris_populate_sampler_key(ice, &key->tex);
}
/**
iris_populate_gs_key(const struct iris_context *ice,
struct brw_gs_prog_key *key)
{
- iris_populate_sampler_key(ice, &key->tex);
}
/**
iris_populate_fs_key(const struct iris_context *ice,
struct brw_wm_prog_key *key)
{
- iris_populate_sampler_key(ice, &key->tex);
-
- /* XXX: dirty flags? */
const struct pipe_framebuffer_state *fb = &ice->state.framebuffer;
const struct iris_depth_stencil_alpha_state *zsa = ice->state.cso_zsa;
const struct iris_rasterizer_state *rast = ice->state.cso_rast;
key->coherent_fb_fetch = true;
- // XXX: uint64_t input_slots_valid; - for >16 inputs
-
// XXX: key->force_dual_color_blend for unigine
// XXX: respect hint for high_quality_derivatives:1;
}
iris_populate_cs_key(const struct iris_context *ice,
struct brw_cs_prog_key *key)
{
- iris_populate_sampler_key(ice, &key->tex);
}
#if 0
pkt.Enable = true; \
\
if (prog_data->total_scratch) { \
- uint32_t scratch_addr = \
+ struct iris_bo *bo = \
iris_get_scratch_space(ice, prog_data->total_scratch, stage); \
+ uint32_t scratch_addr = bo->gtt_offset; \
pkt.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11; \
pkt.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr); \
}
KSP(shader) + brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
if (prog_data->total_scratch) {
- uint32_t scratch_addr =
+ struct iris_bo *bo =
iris_get_scratch_space(ice, prog_data->total_scratch,
MESA_SHADER_FRAGMENT);
+ uint32_t scratch_addr = bo->gtt_offset;
ps.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11;
ps.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr);
}
iris_pack_command(GENX(3DSTATE_PS_EXTRA), psx_state, psx) {
psx.PixelShaderValid = true;
psx.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
- psx.PixelShaderKillsPixel = wm_prog_data->uses_kill;
+ // XXX: alpha test / alpha to coverage :/
+ psx.PixelShaderKillsPixel = wm_prog_data->uses_kill ||
+ wm_prog_data->uses_omask;
psx.AttributeEnable = wm_prog_data->num_varying_inputs != 0;
psx.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
psx.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
#define push_bt_entry(addr) \
assert(addr >= binder_addr); \
+ assert(s < prog_data->binding_table.size_bytes / sizeof(uint32_t)); \
if (!pin_only) bt_map[s++] = (addr) - binder_addr;
+#define bt_assert(section, exists) \
+ if (!pin_only) assert(prog_data->binding_table.section == \
+ (exists) ? s : 0xd0d0d0d0)
+
/**
* Populate the binding table for a given shader stage.
*
if (!shader)
return;
+ UNUSED struct brw_stage_prog_data *prog_data = shader->prog_data;
struct iris_shader_state *shs = &ice->state.shaders[stage];
uint32_t binder_addr = binder->bo->gtt_offset;
}
}
- //assert(prog_data->binding_table.texture_start ==
- //(ice->state.num_textures[stage] ? s : 0xd0d0d0d0));
+ bt_assert(texture_start, info->num_textures > 0);
- for (int i = 0; i < shs->num_textures; i++) {
+ for (int i = 0; i < info->num_textures; i++) {
struct iris_sampler_view *view = shs->textures[i];
uint32_t addr = view ? use_sampler_view(batch, view)
: use_null_surface(batch, ice);
push_bt_entry(addr);
}
+ bt_assert(image_start, info->num_images > 0);
+
for (int i = 0; i < info->num_images; i++) {
uint32_t addr = use_image(batch, ice, shs, i);
push_bt_entry(addr);
const int num_ubos = iris_get_shader_num_ubos(ice, stage);
+ bt_assert(ubo_start, num_ubos > 0);
+
for (int i = 0; i < num_ubos; i++) {
uint32_t addr = use_const_buffer(batch, ice, &shs->constbuf[i]);
push_bt_entry(addr);
}
+ bt_assert(ssbo_start, info->num_abos + info->num_ssbos > 0);
+
/* XXX: st is wasting 16 binding table slots for ABOs. Should add a cap
* for changing nir_lower_atomics_to_ssbos setting and buffer_base offset
* in st_atom_storagebuf.c so it'll compact them into one range, with
#if 0
// XXX: not implemented yet
- assert(prog_data->binding_table.plane_start[1] == 0xd0d0d0d0);
- assert(prog_data->binding_table.plane_start[2] == 0xd0d0d0d0);
+ bt_assert(plane_start[1], ...);
+ bt_assert(plane_start[2], ...);
#endif
}
struct iris_batch *batch,
const struct pipe_draw_info *draw)
{
- // XXX: whack IRIS_SHADER_DIRTY_BINDING_TABLE on new batch
+ struct iris_genx_state *genx = ice->state.genx;
const uint64_t clean = ~ice->state.dirty;
iris_use_optional_res(batch, ice->state.last_res.scissor, false);
}
+ if (ice->state.streamout_active && (clean & IRIS_DIRTY_SO_BUFFERS)) {
+ for (int i = 0; i < 4; i++) {
+ struct iris_stream_output_target *tgt =
+ (void *) ice->state.so_target[i];
+ if (tgt) {
+ iris_use_pinned_bo(batch, iris_resource_bo(tgt->base.buffer),
+ true);
+ iris_use_pinned_bo(batch, iris_resource_bo(tgt->offset.res),
+ true);
+ }
+ }
+ }
+
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
if (!(clean & (IRIS_DIRTY_CONSTANTS_VS << stage)))
continue;
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
if (clean & (IRIS_DIRTY_VS << stage)) {
struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+
if (shader) {
struct iris_bo *bo = iris_resource_bo(shader->assembly.res);
iris_use_pinned_bo(batch, bo, false);
- }
- // XXX: scratch buffer
+ struct brw_stage_prog_data *prog_data = shader->prog_data;
+
+ if (prog_data->total_scratch > 0) {
+ struct iris_bo *bo =
+ iris_get_scratch_space(ice, prog_data->total_scratch, stage);
+ iris_use_pinned_bo(batch, bo, true);
+ }
+ }
}
}
struct iris_resource *zres, *sres;
iris_get_depth_stencil_resources(cso_fb->zsbuf->texture,
&zres, &sres);
- // XXX: might not be writable...
- if (zres)
- iris_use_pinned_bo(batch, zres->bo, true);
- if (sres)
- iris_use_pinned_bo(batch, sres->bo, true);
+ if (zres) {
+ iris_use_pinned_bo(batch, zres->bo,
+ ice->state.depth_writes_enabled);
+ }
+ if (sres) {
+ iris_use_pinned_bo(batch, sres->bo,
+ ice->state.stencil_writes_enabled);
+ }
}
}
}
if (clean & IRIS_DIRTY_VERTEX_BUFFERS) {
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
- for (unsigned i = 0; i < cso->num_buffers; i++) {
- struct iris_resource *res = (void *) cso->resources[i];
- iris_use_pinned_bo(batch, res->bo, false);
+ uint64_t bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ struct pipe_resource *res = genx->vertex_buffers[i].resource;
+ iris_use_pinned_bo(batch, iris_resource_bo(res), false);
}
}
}
if (clean & IRIS_DIRTY_CS) {
struct iris_compiled_shader *shader = ice->shaders.prog[stage];
+
if (shader) {
struct iris_bo *bo = iris_resource_bo(shader->assembly.res);
iris_use_pinned_bo(batch, bo, false);
- }
- // XXX: scratch buffer
+ struct brw_stage_prog_data *prog_data = shader->prog_data;
+
+ if (prog_data->total_scratch > 0) {
+ struct iris_bo *bo =
+ iris_get_scratch_space(ice, prog_data->total_scratch, stage);
+ iris_use_pinned_bo(batch, bo, true);
+ }
+ }
}
}
flush_for_state_base_change(batch);
iris_emit_cmd(batch, GENX(STATE_BASE_ADDRESS), sba) {
- // XXX: sba.SurfaceStateMemoryObjectControlState = MOCS_WB;
+ sba.SurfaceStateMOCS = MOCS_WB;
sba.SurfaceStateBaseAddressModifyEnable = true;
sba.SurfaceStateBaseAddress = ro_bo(binder->bo, 0);
}
}
if (dirty & IRIS_DIRTY_SF_CL_VIEWPORT) {
+ struct pipe_framebuffer_state *cso_fb = &ice->state.framebuffer;
+ uint32_t sf_cl_vp_address;
+ uint32_t *vp_map =
+ stream_state(batch, ice->state.dynamic_uploader,
+ &ice->state.last_res.sf_cl_vp,
+ 4 * ice->state.num_viewports *
+ GENX(SF_CLIP_VIEWPORT_length), 64, &sf_cl_vp_address);
+
+ for (unsigned i = 0; i < ice->state.num_viewports; i++) {
+ const struct pipe_viewport_state *state = &ice->state.viewports[i];
+ float gb_xmin, gb_xmax, gb_ymin, gb_ymax;
+
+ float vp_xmin = viewport_extent(state, 0, -1.0f);
+ float vp_xmax = viewport_extent(state, 0, 1.0f);
+ float vp_ymin = viewport_extent(state, 1, -1.0f);
+ float vp_ymax = viewport_extent(state, 1, 1.0f);
+
+ calculate_guardband_size(cso_fb->width, cso_fb->height,
+ state->scale[0], state->scale[1],
+ state->translate[0], state->translate[1],
+ &gb_xmin, &gb_xmax, &gb_ymin, &gb_ymax);
+
+ iris_pack_state(GENX(SF_CLIP_VIEWPORT), vp_map, vp) {
+ vp.ViewportMatrixElementm00 = state->scale[0];
+ vp.ViewportMatrixElementm11 = state->scale[1];
+ vp.ViewportMatrixElementm22 = state->scale[2];
+ vp.ViewportMatrixElementm30 = state->translate[0];
+ vp.ViewportMatrixElementm31 = state->translate[1];
+ vp.ViewportMatrixElementm32 = state->translate[2];
+ vp.XMinClipGuardband = gb_xmin;
+ vp.XMaxClipGuardband = gb_xmax;
+ vp.YMinClipGuardband = gb_ymin;
+ vp.YMaxClipGuardband = gb_ymax;
+ vp.XMinViewPort = MAX2(vp_xmin, 0);
+ vp.XMaxViewPort = MIN2(vp_xmax, cso_fb->width) - 1;
+ vp.YMinViewPort = MAX2(vp_ymin, 0);
+ vp.YMaxViewPort = MIN2(vp_ymax, cso_fb->height) - 1;
+ }
+
+ vp_map += GENX(SF_CLIP_VIEWPORT_length);
+ }
+
iris_emit_cmd(batch, GENX(3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP), ptr) {
- ptr.SFClipViewportPointer =
- emit_state(batch, ice->state.dynamic_uploader,
- &ice->state.last_res.sf_cl_vp,
- genx->sf_cl_vp, 4 * GENX(SF_CLIP_VIEWPORT_length) *
- ice->state.num_viewports, 64);
+ ptr.SFClipViewportPointer = sf_cl_vp_address;
}
}
- /* XXX: L3 State */
-
- // XXX: this is only flagged at setup, we assume a static configuration
if (dirty & IRIS_DIRTY_URB) {
iris_upload_urb_config(ice, batch);
}
uint32_t dynamic_clip[GENX(3DSTATE_CLIP_length)];
iris_pack_command(GENX(3DSTATE_CLIP), &dynamic_clip, cl) {
+ cl.StatisticsEnable = ice->state.statistics_counters_enabled;
+ cl.ClipMode = cso_rast->rasterizer_discard ? CLIPMODE_REJECT_ALL
+ : CLIPMODE_NORMAL;
if (wm_prog_data->barycentric_interp_modes &
BRW_BARYCENTRIC_NONPERSPECTIVE_BITS)
cl.NonPerspectiveBarycentricEnable = true;
}
- /* XXX: FS program updates needs to flag IRIS_DIRTY_WM */
if (dirty & IRIS_DIRTY_WM) {
struct iris_rasterizer_state *cso = ice->state.cso_rast;
uint32_t dynamic_wm[GENX(3DSTATE_WM_length)];
iris_batch_emit(batch, cso_z->packets, sizeof(cso_z->packets));
if (cso_fb->zsbuf) {
- struct iris_resource *zres = (void *) cso_fb->zsbuf->texture;
- // XXX: depth might not be writable...
- iris_use_pinned_bo(batch, zres->bo, true);
+ struct iris_resource *zres, *sres;
+ iris_get_depth_stencil_resources(cso_fb->zsbuf->texture,
+ &zres, &sres);
+ if (zres) {
+ iris_use_pinned_bo(batch, zres->bo,
+ ice->state.depth_writes_enabled);
+ }
+
+ if (sres) {
+ iris_use_pinned_bo(batch, sres->bo,
+ ice->state.stencil_writes_enabled);
+ }
}
}
}
if (dirty & IRIS_DIRTY_VERTEX_BUFFERS) {
- struct iris_vertex_buffer_state *cso = &ice->state.genx->vertex_buffers;
- const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length);
+ int count = util_bitcount64(ice->state.bound_vertex_buffers);
+
+ if (count) {
+ /* The VF cache designers cut corners, and made the cache key's
+ * <VertexBufferIndex, Memory Address> tuple only consider the bottom
+ * 32 bits of the address. If you have two vertex buffers which get
+ * placed exactly 4 GiB apart and use them in back-to-back draw calls,
+ * you can get collisions (even within a single batch).
+ *
+ * So, we need to do a VF cache invalidate if the buffer for a VB
+ * slot slot changes [48:32] address bits from the previous time.
+ */
+ unsigned flush_flags = 0;
- if (cso->num_buffers > 0) {
- iris_batch_emit(batch, cso->vertex_buffers, sizeof(uint32_t) *
- (1 + vb_dwords * cso->num_buffers));
+ uint64_t bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ uint16_t high_bits = 0;
- for (unsigned i = 0; i < cso->num_buffers; i++) {
- struct iris_resource *res = (void *) cso->resources[i];
- if (res)
+ struct iris_resource *res =
+ (void *) genx->vertex_buffers[i].resource;
+ if (res) {
iris_use_pinned_bo(batch, res->bo, false);
+
+ high_bits = res->bo->gtt_offset >> 32ull;
+ if (high_bits != ice->state.last_vbo_high_bits[i]) {
+ flush_flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+ ice->state.last_vbo_high_bits[i] = high_bits;
+ }
+
+ /* If the buffer was written to by streamout, we may need
+ * to stall so those writes land and become visible to the
+ * vertex fetcher.
+ *
+ * TODO: This may stall more than necessary.
+ */
+ if (res->bind_history & PIPE_BIND_STREAM_OUTPUT)
+ flush_flags |= PIPE_CONTROL_CS_STALL;
+ }
+ }
+
+ if (flush_flags)
+ iris_emit_pipe_control_flush(batch, flush_flags);
+
+ const unsigned vb_dwords = GENX(VERTEX_BUFFER_STATE_length);
+
+ uint32_t *map =
+ iris_get_command_space(batch, 4 * (1 + vb_dwords * count));
+ _iris_pack_command(batch, GENX(3DSTATE_VERTEX_BUFFERS), map, vb) {
+ vb.DWordLength = (vb_dwords * count + 1) - 2;
+ }
+ map += 1;
+
+ bound = ice->state.bound_vertex_buffers;
+ while (bound) {
+ const int i = u_bit_scan64(&bound);
+ memcpy(map, genx->vertex_buffers[i].state,
+ sizeof(uint32_t) * vb_dwords);
+ map += vb_dwords;
}
}
}
*/
iris_use_pinned_bo(batch, ice->state.binder.bo, false);
+ if (!batch->contains_draw) {
+ iris_restore_render_saved_bos(ice, batch, draw);
+ batch->contains_draw = true;
+ }
+
iris_upload_dirty_render_state(ice, batch, draw);
if (draw->index_size > 0) {
draw->count * draw->index_size, 4, draw->index.user,
&offset, &ice->state.last_res.index_buffer);
} else {
+ struct iris_resource *res = (void *) draw->index.resource;
+ res->bind_history |= PIPE_BIND_INDEX_BUFFER;
+
pipe_resource_reference(&ice->state.last_res.index_buffer,
draw->index.resource);
offset = 0;
iris_emit_cmd(batch, GENX(3DSTATE_INDEX_BUFFER), ib) {
ib.IndexFormat = draw->index_size >> 1;
- ib.MOCS = MOCS_WB;
+ ib.MOCS = mocs(bo);
ib.BufferSize = bo->size;
ib.BufferStartingAddress = ro_bo(bo, offset);
}
+
+ /* The VF cache key only uses 32-bits, see vertex buffer comment above */
+ uint16_t high_bits = bo->gtt_offset >> 32ull;
+ if (high_bits != ice->state.last_index_bo_high_bits) {
+ iris_emit_pipe_control_flush(batch, PIPE_CONTROL_VF_CACHE_INVALIDATE);
+ ice->state.last_index_bo_high_bits = high_bits;
+ }
}
#define _3DPRIM_END_OFFSET 0x2420
lri.DataDWord = 0;
}
}
+ } else if (draw->count_from_stream_output) {
+ struct iris_stream_output_target *so =
+ (void *) draw->count_from_stream_output;
+
+ // XXX: avoid if possible
+ iris_emit_pipe_control_flush(batch, PIPE_CONTROL_CS_STALL);
+
+ iris_emit_cmd(batch, GENX(MI_LOAD_REGISTER_MEM), lrm) {
+ lrm.RegisterAddress = CS_GPR(0);
+ lrm.MemoryAddress =
+ ro_bo(iris_resource_bo(so->offset.res), so->offset.offset);
+ }
+ iris_math_div32_gpr0(ice, batch, so->stride);
+ _iris_emit_lrr(batch, _3DPRIM_VERTEX_COUNT, CS_GPR(0));
+
+ _iris_emit_lri(batch, _3DPRIM_START_VERTEX, 0);
+ _iris_emit_lri(batch, _3DPRIM_BASE_VERTEX, 0);
+ _iris_emit_lri(batch, _3DPRIM_START_INSTANCE, 0);
+ _iris_emit_lri(batch, _3DPRIM_INSTANCE_COUNT, draw->instance_count);
}
iris_emit_cmd(batch, GENX(3DPRIMITIVE), prim) {
- prim.StartInstanceLocation = draw->start_instance;
- prim.InstanceCount = draw->instance_count;
- prim.VertexCountPerInstance = draw->count;
prim.VertexAccessType = draw->index_size > 0 ? RANDOM : SEQUENTIAL;
+ prim.PredicateEnable =
+ ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
- // XXX: this is probably bonkers.
- prim.StartVertexLocation = draw->start;
-
- prim.IndirectParameterEnable = draw->indirect != NULL;
-
- if (draw->index_size) {
- prim.BaseVertexLocation += draw->index_bias;
+ if (draw->indirect || draw->count_from_stream_output) {
+ prim.IndirectParameterEnable = true;
} else {
- prim.StartVertexLocation += draw->index_bias;
- }
+ prim.StartInstanceLocation = draw->start_instance;
+ prim.InstanceCount = draw->instance_count;
+ prim.VertexCountPerInstance = draw->count;
- //prim.BaseVertexLocation = ...;
- }
+ // XXX: this is probably bonkers.
+ prim.StartVertexLocation = draw->start;
- if (!batch->contains_draw) {
- iris_restore_render_saved_bos(ice, batch, draw);
- batch->contains_draw = true;
+ if (draw->index_size) {
+ prim.BaseVertexLocation += draw->index_bias;
+ } else {
+ prim.StartVertexLocation += draw->index_bias;
+ }
+
+ //prim.BaseVertexLocation = ...;
+ }
}
}
struct brw_stage_prog_data *prog_data = shader->prog_data;
struct brw_cs_prog_data *cs_prog_data = (void *) prog_data;
- // XXX: L3 configuration not set up for SLM
- assert(prog_data->total_shared == 0);
+ /* Always pin the binder. If we're emitting new binding table pointers,
+ * we need it. If not, we're probably inheriting old tables via the
+ * context, and need it anyway. Since true zero-bindings cases are
+ * practically non-existent, just pin it and avoid last_res tracking.
+ */
+ iris_use_pinned_bo(batch, ice->state.binder.bo, false);
if ((dirty & IRIS_DIRTY_CONSTANTS_CS) && shs->cbuf0_needs_upload)
upload_uniforms(ice, MESA_SHADER_COMPUTE);
iris_emit_cmd(batch, GENX(MEDIA_VFE_STATE), vfe) {
if (prog_data->total_scratch) {
- uint32_t scratch_addr =
+ struct iris_bo *bo =
iris_get_scratch_space(ice, prog_data->total_scratch,
MESA_SHADER_COMPUTE);
vfe.PerThreadScratchSpace = ffs(prog_data->total_scratch) - 11;
- vfe.ScratchSpaceBasePointer = rw_bo(NULL, scratch_addr);
+ vfe.ScratchSpaceBasePointer = rw_bo(bo, 0);
}
vfe.MaximumNumberofThreads =
iris_pack_state(GENX(INTERFACE_DESCRIPTOR_DATA), desc, idd) {
idd.SamplerStatePointer = shs->sampler_table.offset;
idd.BindingTablePointer = binder->bt_offset[MESA_SHADER_COMPUTE];
- idd.ConstantURBEntryReadLength = cs_prog_data->push.per_thread.regs;
- idd.CrossThreadConstantDataReadLength =
- cs_prog_data->push.cross_thread.regs;
}
for (int i = 0; i < GENX(INTERFACE_DESCRIPTOR_DATA_length); i++)
static void
iris_destroy_state(struct iris_context *ice)
{
- iris_free_vertex_buffers(&ice->state.genx->vertex_buffers);
+ struct iris_genx_state *genx = ice->state.genx;
+
+ uint64_t bound_vbs = ice->state.bound_vertex_buffers;
+ while (bound_vbs) {
+ const int i = u_bit_scan64(&bound_vbs);
+ pipe_resource_reference(&genx->vertex_buffers[i].resource, NULL);
+ }
// XXX: unreference resources/surfaces.
for (unsigned i = 0; i < ice->state.framebuffer.nr_cbufs; i++) {
}
free(ice->state.genx);
+ pipe_resource_reference(&ice->state.unbound_tex.res, NULL);
+
pipe_resource_reference(&ice->state.last_res.cc_vp, NULL);
pipe_resource_reference(&ice->state.last_res.sf_cl_vp, NULL);
pipe_resource_reference(&ice->state.last_res.color_calc, NULL);
/* ------------------------------------------------------------------- */
+static void
+iris_load_register_reg32(struct iris_batch *batch, uint32_t dst,
+ uint32_t src)
+{
+ _iris_emit_lrr(batch, dst, src);
+}
+
+static void
+iris_load_register_reg64(struct iris_batch *batch, uint32_t dst,
+ uint32_t src)
+{
+ _iris_emit_lrr(batch, dst, src);
+ _iris_emit_lrr(batch, dst + 4, src + 4);
+}
+
static void
iris_load_register_imm32(struct iris_batch *batch, uint32_t reg,
uint32_t val)
return flags;
}
-// XXX: compute support
-#define IS_COMPUTE_PIPELINE(batch) (batch->engine != I915_EXEC_RENDER)
+#define IS_COMPUTE_PIPELINE(batch) (batch->name == IRIS_BATCH_COMPUTE)
/**
* Emit a series of PIPE_CONTROL commands, taking into account any
ctx->bind_vertex_elements_state = iris_bind_vertex_elements_state;
ctx->delete_blend_state = iris_delete_state;
ctx->delete_depth_stencil_alpha_state = iris_delete_state;
- ctx->delete_fs_state = iris_delete_state;
ctx->delete_rasterizer_state = iris_delete_state;
ctx->delete_sampler_state = iris_delete_state;
ctx->delete_vertex_elements_state = iris_delete_state;
- ctx->delete_tcs_state = iris_delete_state;
- ctx->delete_tes_state = iris_delete_state;
- ctx->delete_gs_state = iris_delete_state;
- ctx->delete_vs_state = iris_delete_state;
ctx->set_blend_color = iris_set_blend_color;
ctx->set_clip_state = iris_set_clip_state;
ctx->set_constant_buffer = iris_set_constant_buffer;
ice->vtbl.update_surface_base_address = iris_update_surface_base_address;
ice->vtbl.upload_compute_state = iris_upload_compute_state;
ice->vtbl.emit_raw_pipe_control = iris_emit_raw_pipe_control;
+ ice->vtbl.load_register_reg32 = iris_load_register_reg32;
+ ice->vtbl.load_register_reg64 = iris_load_register_reg64;
ice->vtbl.load_register_imm32 = iris_load_register_imm32;
ice->vtbl.load_register_imm64 = iris_load_register_imm64;
ice->vtbl.load_register_mem32 = iris_load_register_mem32;
projects / mesa.git / blobdiff