radeonsi: force NaNs to 0
[mesa.git] / src / gallium / drivers / llvmpipe / lp_bld_interp.h
index d273e3f9b9927f4f0c740e04c589f8823342fde5..9029d2a41808e1713650224edfc0aea07a619a48 100644 (file)
@@ -85,7 +85,8 @@ struct lp_build_interp_soa_context
    unsigned mask[1 + PIPE_MAX_SHADER_INPUTS]; /**< TGSI_WRITE_MASK_x */
    enum lp_interp interp[1 + PIPE_MAX_SHADER_INPUTS];
    boolean simple_interp;
-   boolean dynamic_offsets;
+
+   double pos_offset;
 
    LLVMValueRef x;
    LLVMValueRef y;
@@ -96,8 +97,6 @@ struct lp_build_interp_soa_context
    LLVMValueRef dadxaos[1 + PIPE_MAX_SHADER_INPUTS];
    LLVMValueRef dadyaos[1 + PIPE_MAX_SHADER_INPUTS];
 
-   LLVMValueRef oow;
-
    LLVMValueRef attribs[1 + PIPE_MAX_SHADER_INPUTS][TGSI_NUM_CHANNELS];
 
    LLVMValueRef xoffset_store;
@@ -116,25 +115,15 @@ lp_build_interp_soa_init(struct lp_build_interp_soa_context *bld,
                          struct gallivm_state *gallivm,
                          unsigned num_inputs,
                          const struct lp_shader_input *inputs,
+                         boolean pixel_center_integer,
                          LLVMBuilderRef builder,
                          struct lp_type type,
-                         boolean dynamic_offsets,
                          LLVMValueRef a0_ptr,
                          LLVMValueRef dadx_ptr,
                          LLVMValueRef dady_ptr,
                          LLVMValueRef x,
                          LLVMValueRef y);
 
-void
-lp_build_interp_soa_update_inputs(struct lp_build_interp_soa_context *bld,
-                                  struct gallivm_state *gallivm,
-                                  int quad_start_index);
-
-void
-lp_build_interp_soa_update_pos(struct lp_build_interp_soa_context *bld,
-                               struct gallivm_state *gallivm,
-                               int quad__start_index);
-
 void
 lp_build_interp_soa_update_inputs_dyn(struct lp_build_interp_soa_context *bld,
                                       struct gallivm_state *gallivm,