freedreno/a6xx: Disable the core layer-size setup.

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_driver.h

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index ffd53c9cd38edda781143cff4fd41a0dcae1e250..322bdd02557614e3358c0c74d192bd4ea69c355f 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -54,7 +54,7 @@ struct nv50_ir_varying
    ubyte si; /* TGSI semantic index */
 };
 
-#ifdef DEBUG
+#ifndef NDEBUG
 # define NV50_IR_DEBUG_BASIC     (1 << 0)
 # define NV50_IR_DEBUG_VERBOSE   (2 << 0)
 # define NV50_IR_DEBUG_REG_ALLOC (1 << 2)
@@ -73,6 +73,7 @@ struct nv50_ir_prog_symbol
 #define NVISA_GK104_CHIPSET    0xe0
 #define NVISA_GK20A_CHIPSET    0xea
 #define NVISA_GM107_CHIPSET    0x110
+#define NVISA_GM200_CHIPSET    0x120
 
 struct nv50_ir_prog_info
 {
@@ -82,6 +83,7 @@ struct nv50_ir_prog_info
 
    uint8_t optLevel; /* optimization level (0 to 3) */
    uint8_t dbgFlags;
+   bool omitLineNum; /* only used for printing the prog when dbgFlags is set */
 
    struct {
       int16_t maxGPR;     /* may be -1 if none used */
@@ -121,7 +123,6 @@ struct nv50_ir_prog_info
          bool usesDrawParameters;
       } vp;
       struct {
-         uint8_t inputPatchSize;
          uint8_t outputPatchSize;
          uint8_t partitioning;    /* PIPE_TESS_PART */
          int8_t winding;          /* +1 (clockwise) / -1 (counter-clockwise) */
@@ -144,6 +145,7 @@ struct nv50_ir_prog_info
          bool persampleInvocation;
          bool usesSampleMaskIn;
          bool readsFramebuffer;
+         bool readsSampleLocations;
       } fp;
       struct {
          uint32_t inputOffset; /* base address for user args */
@@ -179,6 +181,7 @@ struct nv50_ir_prog_info
       uint16_t texBindBase;      /* base address for tex handles (nve4) */
       uint16_t fbtexBindBase;    /* base address for fbtex handle (nve4) */
       uint16_t suInfoBase;       /* base address for surface info (nve4) */
+      uint16_t bindlessBase;     /* base address for bindless image info (nve4) */
       uint16_t bufInfoBase;      /* base address for buffer info */
       uint16_t sampleInfoBase;   /* base address for sample positions */
       uint8_t msInfoCBSlot;      /* cX[] used for multisample info */