nv50/ir: teach insnCanLoad() about SHLADD

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_ra.cpp

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 5bb6f7849b1709811b7e07117a4b5b133caaf8bd..2d3486ba2bc2dbf903f4be3e9cc627b909bfde14 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -969,6 +969,7 @@ GCRA::coalesce(ArrayList& insns)
    case 0x100:
    case 0x110:
    case 0x120:
+   case 0x130:
       ret = doCoalesce(insns, JOIN_MASK_UNION);
       break;
    default:
@@ -2092,8 +2093,29 @@ RegAlloc::InsertConstraintsPass::texConstraintGM107(TexInstruction *tex)
       textureMask(tex);
    condenseDefs(tex);
 
-   if (tex->op == OP_SUSTB || tex->op == OP_SUSTP) {
-      condenseSrcs(tex, 3, (3 + typeSizeof(tex->dType) / 4) - 1);
+   if (isSurfaceOp(tex->op)) {
+      int s = tex->tex.target.getDim() +
+         (tex->tex.target.isArray() || tex->tex.target.isCube());
+      int n = 0;
+
+      switch (tex->op) {
+      case OP_SUSTB:
+      case OP_SUSTP:
+         n = 4;
+         break;
+      case OP_SUREDB:
+      case OP_SUREDP:
+         if (tex->subOp == NV50_IR_SUBOP_ATOM_CAS)
+            n = 2;
+         break;
+      default:
+         break;
+      }
+
+      if (s > 1)
+         condenseSrcs(tex, 0, s - 1);
+      if (n > 1)
+         condenseSrcs(tex, 1, n); // do not condense the tex handle
    } else
    if (isTextureOp(tex->op)) {
       if (tex->op != OP_TXQ) {
@@ -2234,6 +2256,7 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
             break;
          case 0x110:
          case 0x120:
+         case 0x130:
             texConstraintGM107(tex);
             break;
          default: