nvc0/ir: check that the image format doesn't mismatch

[mesa.git] / src / gallium / drivers / nouveau / codegen / nv50_ir_target.h

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
index 9913ca13ddda60a46cc6637225da88d25c4271bd..e6e1912adae023e3e74b8a49aae9d2d680c73170 100644 (file)
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target.h
@@ -58,6 +58,23 @@ struct RelocInfo
    RelocEntry entry[0];
 };
 
+struct InterpEntry
+{
+   InterpEntry(int ipa, int reg, int loc) : ipa(ipa), reg(reg), loc(loc) {}
+   uint32_t ipa:4; // SC mode used to identify colors
+   uint32_t reg:8; // The reg used for perspective division
+   uint32_t loc:20; // Let's hope we don't have more than 1M-sized shaders
+};
+
+typedef void (*InterpApply)(const InterpEntry*, uint32_t*, bool, bool);
+
+struct InterpInfo
+{
+   uint32_t count;
+   InterpApply apply;
+   InterpEntry entry[0];
+};
+
 class CodeEmitter
 {
 public:
@@ -78,7 +95,10 @@ public:
 
    inline void *getRelocInfo() const { return relocInfo; }
 
-   void prepareEmission(Program *);
+   bool addInterp(int ipa, int reg, InterpApply apply);
+   inline void *getInterpInfo() const { return interpInfo; }
+
+   virtual void prepareEmission(Program *);
    virtual void prepareEmission(Function *);
    virtual void prepareEmission(BasicBlock *);
 
@@ -92,6 +112,7 @@ protected:
    uint32_t codeSizeLimit;
 
    RelocInfo *relocInfo;
+   InterpInfo *interpInfo;
 };
 
 
@@ -120,7 +141,7 @@ enum OpClass
 class Target
 {
 public:
-   Target(bool j, bool s) : joinAnterior(j), hasSWSched(s) { }
+   Target(bool m, bool j, bool s) : hasJoin(m), joinAnterior(j), hasSWSched(s) { }
    virtual ~Target() { }
 
    static Target *create(uint32_t chipset);
@@ -151,8 +172,8 @@ public:
       uint8_t srcNr;
       uint8_t srcMods[3];
       uint8_t dstMods;
-      uint8_t srcFiles[3];
-      uint8_t dstFiles;
+      uint16_t srcFiles[3];
+      uint16_t dstFiles;
       unsigned int minEncSize  : 4;
       unsigned int vector      : 1;
       unsigned int predicate   : 1;
@@ -170,6 +191,8 @@ public:
 
    virtual bool insnCanLoad(const Instruction *insn, int s,
                             const Instruction *ld) const = 0;
+   virtual bool insnCanLoadOffset(const Instruction *insn, int s,
+                                  int offset) const = 0;
    virtual bool isOpSupported(operation, DataType) const = 0;
    virtual bool isAccessSupported(DataFile, DataType) const = 0;
    virtual bool isModSupported(const Instruction *,
@@ -192,11 +215,12 @@ public:
    virtual uint32_t getSVAddress(DataFile, const Symbol *) const = 0;
 
 public:
+   const bool hasJoin;      // true if instructions have a join modifier
    const bool joinAnterior; // true if join is executed before the op
    const bool hasSWSched;   // true if code should provide scheduling data
 
-   static const uint8_t operationSrcNr[OP_LAST + 1];
-   static const OpClass operationClass[OP_LAST + 1];
+   static const uint8_t operationSrcNr[];
+   static const OpClass operationClass[];
 
    static inline uint8_t getOpSrcNr(operation op)
    {