gv100/ir: fix atom cas

[mesa.git] / src / gallium / drivers / nouveau / nouveau_winsys.h

diff --git a/src/gallium/drivers/nouveau/nouveau_winsys.h b/src/gallium/drivers/nouveau/nouveau_winsys.h
index bed014b9ce084d0c16cd9c42b7cc08d33904bffe..e0ed0af3eaa3fa2013d142efcc4618999f573239 100644 (file)
--- a/src/gallium/drivers/nouveau/nouveau_winsys.h
+++ b/src/gallium/drivers/nouveau/nouveau_winsys.h
@@ -2,34 +2,91 @@
 #define NOUVEAU_WINSYS_H
 
 #include <stdint.h>
-#include "util/u_simple_screen.h"
+#include <inttypes.h>
+
 #include "pipe/p_defines.h"
 
-#include "nouveau/nouveau_bo.h"
-#include "nouveau/nouveau_channel.h"
-#include "nouveau/nouveau_class.h"
-#include "nouveau/nouveau_device.h"
-#include "nouveau/nouveau_grobj.h"
-#include "nouveau/nouveau_notifier.h"
-#include "nouveau/nouveau_resource.h"
-#include "nouveau/nouveau_pushbuf.h"
+#include "drm-uapi/drm.h"
+#include <nouveau.h>
+
+#ifndef NV04_PFIFO_MAX_PACKET_LEN
+#define NV04_PFIFO_MAX_PACKET_LEN 2047
+#endif
+
+#define NOUVEAU_MIN_BUFFER_MAP_ALIGN      64
+#define NOUVEAU_MIN_BUFFER_MAP_ALIGN_MASK (NOUVEAU_MIN_BUFFER_MAP_ALIGN - 1)
+
+static inline uint32_t
+PUSH_AVAIL(struct nouveau_pushbuf *push)
+{
+   return push->end - push->cur;
+}
+
+static inline bool
+PUSH_SPACE(struct nouveau_pushbuf *push, uint32_t size)
+{
+   /* Provide a buffer so that fences always have room to be emitted */
+   size += 8;
+   if (PUSH_AVAIL(push) < size)
+      return nouveau_pushbuf_space(push, size, 0, 0) == 0;
+   return true;
+}
+
+static inline void
+PUSH_DATA(struct nouveau_pushbuf *push, uint32_t data)
+{
+   *push->cur++ = data;
+}
+
+static inline void
+PUSH_DATAp(struct nouveau_pushbuf *push, const void *data, uint32_t size)
+{
+   memcpy(push->cur, data, size * 4);
+   push->cur += size;
+}
+
+static inline void
+PUSH_DATAf(struct nouveau_pushbuf *push, float f)
+{
+   union { float f; uint32_t i; } u;
+   u.f = f;
+   PUSH_DATA(push, u.i);
+}
+
+static inline void
+PUSH_KICK(struct nouveau_pushbuf *push)
+{
+   nouveau_pushbuf_kick(push, push->channel);
+}
+
+
+#define NOUVEAU_RESOURCE_FLAG_LINEAR   (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
+#define NOUVEAU_RESOURCE_FLAG_DRV_PRIV (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
 
-#define NOUVEAU_CAP_HW_VTXBUF (0xbeef0000)
-#define NOUVEAU_CAP_HW_IDXBUF (0xbeef0001)
+static inline uint32_t
+nouveau_screen_transfer_flags(unsigned pipe)
+{
+   uint32_t flags = 0;
 
-#define NOUVEAU_TEXTURE_USAGE_LINEAR (1 << 16)
+   if (!(pipe & PIPE_TRANSFER_UNSYNCHRONIZED)) {
+      if (pipe & PIPE_TRANSFER_READ)
+         flags |= NOUVEAU_BO_RD;
+      if (pipe & PIPE_TRANSFER_WRITE)
+         flags |= NOUVEAU_BO_WR;
+      if (pipe & PIPE_TRANSFER_DONTBLOCK)
+         flags |= NOUVEAU_BO_NOBLOCK;
+   }
 
-#define NOUVEAU_BUFFER_USAGE_TEXTURE  (1 << 16)
-#define NOUVEAU_BUFFER_USAGE_ZETA     (1 << 17)
-#define NOUVEAU_BUFFER_USAGE_TRANSFER (1 << 18)
+   return flags;
+}
 
-/* use along with GPU_WRITE for 2D-only writes */
-#define NOUVEAU_BUFFER_USAGE_NO_RENDER (1 << 19)
+extern struct nouveau_screen *
+nv30_screen_create(struct nouveau_device *);
 
-extern struct pipe_screen *
-nvfx_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
+extern struct nouveau_screen *
+nv50_screen_create(struct nouveau_device *);
 
-extern struct pipe_screen *
-nv50_screen_create(struct pipe_winsys *ws, struct nouveau_device *);
+extern struct nouveau_screen *
+nvc0_screen_create(struct nouveau_device *);
 
 #endif