const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
switch (param) {
- case PIPE_CAP_MAX_COMBINED_SAMPLERS:
- return 64;
+ /* non-boolean caps */
case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
return 14;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
return 14;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 512;
+ case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MIN_TEXEL_OFFSET:
return -8;
+ case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
case PIPE_CAP_MAX_TEXEL_OFFSET:
return 7;
+ case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
+ return 65536;
+ case PIPE_CAP_GLSL_FEATURE_LEVEL:
+ return 330;
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ return 8;
+ case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
+ return 1;
+ case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+ return 4;
+ case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+ case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+ return 64;
+ case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
+ case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
+ return 1024;
+ case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
+ return 256;
+ case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
+ return 1; /* 256 for binding as RT, but that's not possible in GL */
+ case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
+ return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
+ case PIPE_CAP_MAX_VIEWPORTS:
+ return NV50_MAX_VIEWPORTS;
+ case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
+ return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
+ case PIPE_CAP_ENDIANNESS:
+ return PIPE_ENDIAN_LITTLE;
+ case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+ return (class_3d >= NVA3_3D_CLASS) ? 4 : 0;
+
+ /* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_ANISOTROPIC_FILTER:
- case PIPE_CAP_SCALED_RESOLVE:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
- return 1;
- case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
- return 65536;
- case PIPE_CAP_SEAMLESS_CUBE_MAP:
- return nv50_screen(pscreen)->tesla->oclass >= NVA0_3D_CLASS;
- case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- return 0;
- case PIPE_CAP_CUBE_MAP_ARRAY:
- return 0;
- /*
- return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
- */
+ case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_POINT_SPRITE:
- return 1;
case PIPE_CAP_SM3:
- return 1;
- case PIPE_CAP_GLSL_FEATURE_LEVEL:
- return 140;
- case PIPE_CAP_MAX_RENDER_TARGETS:
- return 8;
- case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
- return 1;
case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_VERTEX_COLOR_CLAMPED:
- return 1;
case PIPE_CAP_QUERY_TIMESTAMP:
case PIPE_CAP_QUERY_TIME_ELAPSED:
case PIPE_CAP_OCCLUSION_QUERY:
- return 1;
- case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
- return 4;
- case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
- case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
- return 64;
- case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
- return (class_3d >= NVA0_3D_CLASS) ? 1 : 0;
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_INDEP_BLEND_ENABLE:
- return 1;
- case PIPE_CAP_INDEP_BLEND_FUNC:
- return nv50_screen(pscreen)->tesla->oclass >= NVA3_3D_CLASS;
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
- return 1;
- case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
- case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
- return 0;
- case PIPE_CAP_SHADER_STENCIL_EXPORT:
- return 0;
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_TEXTURE_BARRIER:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_START_INSTANCE:
- return 1;
- case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
- return 0; /* state trackers will know better */
case PIPE_CAP_USER_CONSTANT_BUFFERS:
case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_VERTEX_BUFFERS:
+ case PIPE_CAP_TEXTURE_MULTISAMPLE:
+ case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return 1;
- case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
- return 256;
- case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 1; /* 256 for binding as RT, but that's not possible in GL */
- case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
- return NOUVEAU_MIN_BUFFER_MAP_ALIGN;
+ case PIPE_CAP_SEAMLESS_CUBE_MAP:
+ return 1; /* class_3d >= NVA0_3D_CLASS; */
+ /* supported on nva0+ */
+ case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ return class_3d >= NVA0_3D_CLASS;
+ /* supported on nva3+ */
+ case PIPE_CAP_CUBE_MAP_ARRAY:
+ case PIPE_CAP_INDEP_BLEND_FUNC:
+ case PIPE_CAP_TEXTURE_QUERY_LOD:
+ case PIPE_CAP_SAMPLE_SHADING:
+ return class_3d >= NVA3_3D_CLASS;
+
+ /* unsupported caps */
+ case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+ case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+ case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+ case PIPE_CAP_SHADER_STENCIL_EXPORT:
+ case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_TGSI_TEXCOORD:
- case PIPE_CAP_TEXTURE_MULTISAMPLE:
- return 0;
- case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
- return 1;
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
- return 0;
- case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
- return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
- case PIPE_CAP_ENDIANNESS:
- return PIPE_ENDIAN_LITTLE;
case PIPE_CAP_TGSI_VS_LAYER:
- return 0;
- default:
- NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
+ case PIPE_CAP_TEXTURE_GATHER_SM5:
+ case PIPE_CAP_FAKE_SW_MSAA:
+ case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
+ case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
+ case PIPE_CAP_COMPUTE:
return 0;
}
+
+ NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
+ return 0;
}
static int
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return 4.0f;
- default:
- NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
+ case PIPE_CAPF_GUARD_BAND_LEFT:
+ case PIPE_CAPF_GUARD_BAND_TOP:
return 0.0f;
+ case PIPE_CAPF_GUARD_BAND_RIGHT:
+ case PIPE_CAPF_GUARD_BAND_BOTTOM:
+ return 0.0f; /* that or infinity */
}
+
+ NOUVEAU_ERR("unknown PIPE_CAPF %d\n", param);
+ return 0.0f;
}
static void
{
struct nv50_screen *screen = nv50_screen(pscreen);
+ if (!nouveau_drm_screen_unref(&screen->base))
+ return;
+
if (screen->base.fence.current) {
- nouveau_fence_wait(screen->base.fence.current);
- nouveau_fence_ref (NULL, &screen->base.fence.current);
+ struct nouveau_fence *current = NULL;
+
+ /* nouveau_fence_wait will create a new current fence, so wait on the
+ * _current_ one, and remove both.
+ */
+ nouveau_fence_ref(screen->base.fence.current, ¤t);
+ nouveau_fence_wait(current);
+ nouveau_fence_ref(NULL, ¤t);
+ nouveau_fence_ref(NULL, &screen->base.fence.current);
}
if (screen->base.pushbuf)
screen->base.pushbuf->user_priv = NULL;
PUSH_DATA (push, 0);
BEGIN_NV04(push, SUBC_2D(0x0888), 1);
PUSH_DATA (push, 1);
+ BEGIN_NV04(push, NV50_2D(COND_MODE), 1);
+ PUSH_DATA (push, NV50_2D_COND_MODE_ALWAYS);
BEGIN_NV04(push, SUBC_3D(NV01_SUBCHAN_OBJECT), 1);
PUSH_DATA (push, screen->tesla->handle);
BEGIN_NV04(push, NV50_3D(CB_DEF_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->uniforms->offset + (3 << 16));
PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
- PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
+ PUSH_DATA (push, (NV50_CB_AUX << 16) | (NV50_CB_AUX_SIZE & 0xffff));
BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
/* return { 0.0, 0.0, 0.0, 0.0 } on out-of-bounds vtxbuf access */
BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
- PUSH_DATA (push, ((1 << 9) << 6) | NV50_CB_AUX);
+ PUSH_DATA (push, (NV50_CB_AUX_RUNOUT_OFFSET << (8 - 2)) | NV50_CB_AUX);
BEGIN_NI04(push, NV50_3D(CB_DATA(0)), 4);
PUSH_DATAf(push, 0.0f);
PUSH_DATAf(push, 0.0f);
PUSH_DATAf(push, 0.0f);
PUSH_DATAf(push, 0.0f);
BEGIN_NV04(push, NV50_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + (1 << 9));
- PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + (1 << 9));
+ PUSH_DATAh(push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
+ PUSH_DATA (push, screen->uniforms->offset + (3 << 16) + NV50_CB_AUX_RUNOUT_OFFSET);
+
+ nv50_upload_ms_info(push);
/* max TIC (bits 4:8) & TSC bindings, per program type */
for (i = 0; i < 3; ++i) {
BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
PUSH_DATA (push, 1);
- BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(0)), 2);
- PUSH_DATAf(push, 0.0f);
- PUSH_DATAf(push, 1.0f);
+ for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
+ BEGIN_NV04(push, NV50_3D(DEPTH_RANGE_NEAR(i)), 2);
+ PUSH_DATAf(push, 0.0f);
+ PUSH_DATAf(push, 1.0f);
+ BEGIN_NV04(push, NV50_3D(VIEWPORT_HORIZ(i)), 2);
+ PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 8192 << 16);
+ }
BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
#ifdef NV50_SCISSORS_CLIPPING
/* We use scissors instead of exact view volume clipping,
* so they're always enabled.
*/
- BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(0)), 3);
- PUSH_DATA (push, 1);
- PUSH_DATA (push, 8192 << 16);
- PUSH_DATA (push, 8192 << 16);
+ for (i = 0; i < NV50_MAX_VIEWPORTS; i++) {
+ BEGIN_NV04(push, NV50_3D(SCISSOR_ENABLE(i)), 3);
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 8192 << 16);
+ PUSH_DATA (push, 8192 << 16);
+ }
BEGIN_NV04(push, NV50_3D(RASTERIZE_ENABLE), 1);
PUSH_DATA (push, 1);
goto fail;
}
+ /* This over-allocates by a page. The GP, which would execute at the end of
+ * the last page, would trigger faults. The going theory is that it
+ * prefetches up to a certain amount.
+ */
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 << 16,
- 3 << NV50_CODE_BO_SIZE_LOG2, NULL, &screen->code);
+ (3 << NV50_CODE_BO_SIZE_LOG2) + 0x1000,
+ NULL, &screen->code);
if (ret) {
NOUVEAU_ERR("Failed to allocate code bo: %d\n", ret);
goto fail;
projects / mesa.git / blobdiff