addr = mt->base.address;
- if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
- mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
+
+ if (mt->base.base.array_size > 1) {
+ /* there doesn't seem to be a base layer field in TIC */
addr += view->pipe.u.tex.first_layer * mt->layer_stride;
depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
- } else {
- depth = mt->base.base.depth0;
}
tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
tic[3] = mt->level[0].pitch;
tic[4] = mt->base.base.width0;
- tic[5] = (1 << 16) | mt->base.base.height0;
+ tic[5] = (1 << 16) | (mt->base.base.height0);
}
tic[6] =
tic[7] = 0;
BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
PUSH_DATA (push, (i << 1) | 0);
}
+ if (nv50->num_textures[s]) {
+ BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
+ PUSH_DATA (push, ((NV50_CB_AUX_TEX_MS_OFFSET + 16 * s * 2 * 4) << (8 - 2)) | NV50_CB_AUX);
+ BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
+ for (i = 0; i < nv50->num_textures[s]; i++) {
+ struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]);
+ struct nv50_miptree *res;
+
+ if (!tic) {
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 0);
+ continue;
+ }
+ res = nv50_miptree(tic->pipe.texture);
+ PUSH_DATA (push, res->ms_x);
+ PUSH_DATA (push, res->ms_y);
+ }
+ }
nv50->state.num_textures[s] = nv50->num_textures[s];
return need_flush;
boolean need_flush;
need_flush = nv50_validate_tic(nv50, 0);
+ need_flush |= nv50_validate_tic(nv50, 1);
need_flush |= nv50_validate_tic(nv50, 2);
if (need_flush) {
unsigned i;
boolean need_flush = FALSE;
+ assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nv50->num_samplers[s]; ++i) {
struct nv50_tsc_entry *tsc = nv50_tsc_entry(nv50->samplers[s][i]);
boolean need_flush;
need_flush = nv50_validate_tsc(nv50, 0);
+ need_flush |= nv50_validate_tsc(nv50, 1);
need_flush |= nv50_validate_tsc(nv50, 2);
if (need_flush) {
PUSH_DATA (nv50->base.pushbuf, 0);
}
}
+
+/* There can be up to 4 different MS levels (1, 2, 4, 8). To simplify the
+ * shader logic, allow each one to take up 8 offsets.
+ */
+#define COMBINE(x, y) x, y
+#define DUMMY 0, 0
+static const uint32_t msaa_sample_xy_offsets[] = {
+ /* MS1 */
+ COMBINE(0, 0),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS2 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS4 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ COMBINE(0, 1),
+ COMBINE(1, 1),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS8 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ COMBINE(0, 1),
+ COMBINE(1, 1),
+ COMBINE(2, 0),
+ COMBINE(3, 0),
+ COMBINE(2, 1),
+ COMBINE(3, 1),
+};
+
+void nv50_upload_ms_info(struct nouveau_pushbuf *push)
+{
+ BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
+ PUSH_DATA (push, (NV50_CB_AUX_MS_OFFSET << (8 - 2)) | NV50_CB_AUX);
+ BEGIN_NI04(push, NV50_3D(CB_DATA(0)), Elements(msaa_sample_xy_offsets));
+ PUSH_DATAp(push, msaa_sample_xy_offsets, Elements(msaa_sample_xy_offsets));
+}