Merge remote-tracking branch 'origin/master' into vulkan
[mesa.git] / src / gallium / drivers / nouveau / nv50 / nv50_tex.c
index fc6374d1b1b3dfffc14f3c026929d96834e6bc8a..4b69c3bd5048d008dca743c356b8dc74ce6e080a 100644 (file)
 
 #include "nv50/nv50_context.h"
 #include "nv50/nv50_resource.h"
-#include "nv50/nv50_texture.xml.h"
-#include "nv50/nv50_defs.xml.h"
+#include "nv50/g80_texture.xml.h"
+#include "nv50/g80_defs.xml.h"
 
 #include "util/u_format.h"
 
-#define NV50_TIC_0_SWIZZLE__MASK                      \
-   (NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK |   \
-    NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
-
 static inline uint32_t
-nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
+nv50_tic_swizzle(const struct nv50_format *fmt, unsigned swz, bool tex_int)
 {
    switch (swz) {
-   case PIPE_SWIZZLE_RED:
-      return (tc & NV50_TIC_0_MAPR__MASK) >> NV50_TIC_0_MAPR__SHIFT;
-   case PIPE_SWIZZLE_GREEN:
-      return (tc & NV50_TIC_0_MAPG__MASK) >> NV50_TIC_0_MAPG__SHIFT;
-   case PIPE_SWIZZLE_BLUE:
-      return (tc & NV50_TIC_0_MAPB__MASK) >> NV50_TIC_0_MAPB__SHIFT;
-   case PIPE_SWIZZLE_ALPHA:
-      return (tc & NV50_TIC_0_MAPA__MASK) >> NV50_TIC_0_MAPA__SHIFT;
+   case PIPE_SWIZZLE_RED  : return fmt->tic.src_x;
+   case PIPE_SWIZZLE_GREEN: return fmt->tic.src_y;
+   case PIPE_SWIZZLE_BLUE : return fmt->tic.src_z;
+   case PIPE_SWIZZLE_ALPHA: return fmt->tic.src_w;
    case PIPE_SWIZZLE_ONE:
-      return tex_int ? NV50_TIC_MAP_ONE_INT : NV50_TIC_MAP_ONE_FLOAT;
+      return tex_int ? G80_TIC_SOURCE_ONE_INT : G80_TIC_SOURCE_ONE_FLOAT;
    case PIPE_SWIZZLE_ZERO:
    default:
-      return NV50_TIC_MAP_ZERO;
+      return G80_TIC_SOURCE_ZERO;
    }
 }
 
@@ -73,6 +65,7 @@ nv50_create_texture_view(struct pipe_context *pipe,
 {
    const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d;
    const struct util_format_description *desc;
+   const struct nv50_format *fmt;
    uint64_t addr;
    uint32_t *tic;
    uint32_t swz[4];
@@ -100,19 +93,23 @@ nv50_create_texture_view(struct pipe_context *pipe,
 
    /* TIC[0] */
 
-   tic[0] = nv50_format_table[view->pipe.format].tic;
+   fmt = &nv50_format_table[view->pipe.format];
 
    tex_int = util_format_is_pure_integer(view->pipe.format);
 
-   swz[0] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_r, tex_int);
-   swz[1] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_g, tex_int);
-   swz[2] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_b, tex_int);
-   swz[3] = nv50_tic_swizzle(tic[0], view->pipe.swizzle_a, tex_int);
-   tic[0] = (tic[0] & ~NV50_TIC_0_SWIZZLE__MASK) |
-      (swz[0] << NV50_TIC_0_MAPR__SHIFT) |
-      (swz[1] << NV50_TIC_0_MAPG__SHIFT) |
-      (swz[2] << NV50_TIC_0_MAPB__SHIFT) |
-      (swz[3] << NV50_TIC_0_MAPA__SHIFT);
+   swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
+   swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
+   swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
+   swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
+   tic[0] = (fmt->tic.format << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
+            (fmt->tic.type_r << G80_TIC_0_R_DATA_TYPE__SHIFT) |
+            (fmt->tic.type_g << G80_TIC_0_G_DATA_TYPE__SHIFT) |
+            (fmt->tic.type_b << G80_TIC_0_B_DATA_TYPE__SHIFT) |
+            (fmt->tic.type_a << G80_TIC_0_A_DATA_TYPE__SHIFT) |
+            (swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
+            (swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
+            (swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
+            (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
 
    addr = mt->base.address;
 
@@ -124,24 +121,24 @@ nv50_create_texture_view(struct pipe_context *pipe,
       depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
    }
 
-   tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
+   tic[2] = 0x10001000 | G80_TIC_2_BORDER_SOURCE_COLOR;
 
    if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
-      tic[2] |= NV50_TIC_2_COLORSPACE_SRGB;
+      tic[2] |= G80_TIC_2_SRGB_CONVERSION;
 
    if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
-      tic[2] |= NV50_TIC_2_NORMALIZED_COORDS;
+      tic[2] |= G80_TIC_2_NORMALIZED_COORDS;
 
    if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
       if (target == PIPE_BUFFER) {
          addr += view->pipe.u.buf.first_element * desc->block.bits / 8;
-         tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_BUFFER;
+         tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER;
          tic[3] = 0;
          tic[4] = /* width */
             view->pipe.u.buf.last_element - view->pipe.u.buf.first_element + 1;
          tic[5] = 0;
       } else {
-         tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
+         tic[2] |= G80_TIC_2_LAYOUT_PITCH | G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
          tic[3] = mt->level[0].pitch;
          tic[4] = mt->base.base.width0;
          tic[5] = (1 << 16) | (mt->base.base.height0);
@@ -162,38 +159,37 @@ nv50_create_texture_view(struct pipe_context *pipe,
 
    switch (target) {
    case PIPE_TEXTURE_1D:
-      tic[2] |= NV50_TIC_2_TARGET_1D;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D;
       break;
    case PIPE_TEXTURE_2D:
-      tic[2] |= NV50_TIC_2_TARGET_2D;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D;
       break;
    case PIPE_TEXTURE_RECT:
-      tic[2] |= NV50_TIC_2_TARGET_RECT;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
       break;
    case PIPE_TEXTURE_3D:
-      tic[2] |= NV50_TIC_2_TARGET_3D;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_THREE_D;
       break;
    case PIPE_TEXTURE_CUBE:
       depth /= 6;
-      tic[2] |= NV50_TIC_2_TARGET_CUBE;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBEMAP;
       break;
    case PIPE_TEXTURE_1D_ARRAY:
-      tic[2] |= NV50_TIC_2_TARGET_1D_ARRAY;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_ARRAY;
       break;
    case PIPE_TEXTURE_2D_ARRAY:
-      tic[2] |= NV50_TIC_2_TARGET_2D_ARRAY;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_TWO_D_ARRAY;
       break;
    case PIPE_TEXTURE_CUBE_ARRAY:
       depth /= 6;
-      tic[2] |= NV50_TIC_2_TARGET_CUBE_ARRAY;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_CUBE_ARRAY;
       break;
    case PIPE_BUFFER:
       assert(0); /* should be linear and handled above ! */
-      tic[2] |= NV50_TIC_2_TARGET_BUFFER | NV50_TIC_2_LINEAR;
+      tic[2] |= G80_TIC_2_TEXTURE_TYPE_ONE_D_BUFFER | G80_TIC_2_LAYOUT_PITCH;
       break;
    default:
-      NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
-      return false;
+      unreachable("unexpected/invalid texture target");
    }
 
    tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000;
@@ -203,9 +199,9 @@ nv50_create_texture_view(struct pipe_context *pipe,
    tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
    tic[5] |= depth << 16;
    if (class_3d > NV50_3D_CLASS)
-      tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+      tic[5] |= mt->base.base.last_level << G80_TIC_5_MAP_MIP_LEVEL__SHIFT;
    else
-      tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+      tic[5] |= view->pipe.u.tex.last_level << G80_TIC_5_MAP_MIP_LEVEL__SHIFT;
 
    tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
 
@@ -214,13 +210,33 @@ nv50_create_texture_view(struct pipe_context *pipe,
    else
       tic[7] = 0;
 
-   if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS)))
+   if (unlikely(!(tic[2] & G80_TIC_2_NORMALIZED_COORDS)))
       if (mt->base.base.last_level)
-         tic[5] &= ~NV50_TIC_5_LAST_LEVEL__MASK;
+         tic[5] &= ~G80_TIC_5_MAP_MIP_LEVEL__MASK;
 
    return &view->pipe;
 }
 
+static void
+nv50_update_tic(struct nv50_context *nv50, struct nv50_tic_entry *tic,
+                struct nv04_resource *res)
+{
+   uint64_t address = res->address;
+   if (res->base.target != PIPE_BUFFER)
+      return;
+   address += tic->pipe.u.buf.first_element *
+      util_format_get_blocksize(tic->pipe.format);
+   if (tic->tic[1] == (uint32_t)address &&
+       (tic->tic[2] & 0xff) == address >> 32)
+      return;
+
+   nv50_screen_tic_unlock(nv50->screen, tic);
+   tic->id = -1;
+   tic->tic[1] = address;
+   tic->tic[2] &= 0xffffff00;
+   tic->tic[2] |= address >> 32;
+}
+
 static bool
 nv50_validate_tic(struct nv50_context *nv50, int s)
 {
@@ -240,12 +256,13 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
          continue;
       }
       res = &nv50_miptree(tic->pipe.texture)->base;
+      nv50_update_tic(nv50, tic, res);
 
       if (tic->id < 0) {
          tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
 
          BEGIN_NV04(push, NV50_2D(DST_FORMAT), 2);
-         PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+         PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
          PUSH_DATA (push, 1);
          BEGIN_NV04(push, NV50_2D(DST_PITCH), 5);
          PUSH_DATA (push, 262144);
@@ -255,7 +272,7 @@ nv50_validate_tic(struct nv50_context *nv50, int s)
          PUSH_DATA (push, txc->offset);
          BEGIN_NV04(push, NV50_2D(SIFC_BITMAP_ENABLE), 2);
          PUSH_DATA (push, 0);
-         PUSH_DATA (push, NV50_SURFACE_FORMAT_R8_UNORM);
+         PUSH_DATA (push, G80_SURFACE_FORMAT_R8_UNORM);
          BEGIN_NV04(push, NV50_2D(SIFC_WIDTH), 10);
          PUSH_DATA (push, 32);
          PUSH_DATA (push, 1);
@@ -344,6 +361,7 @@ nv50_validate_tsc(struct nv50_context *nv50, int s)
          PUSH_DATA (push, (i << 4) | 0);
          continue;
       }
+      nv50->seamless_cube_map = tsc->seamless_cube_map;
       if (tsc->id < 0) {
          tsc->id = nv50_screen_tsc_alloc(nv50->screen, tsc);