(NV50_TIC_0_MAPA__MASK | NV50_TIC_0_MAPB__MASK | \
NV50_TIC_0_MAPG__MASK | NV50_TIC_0_MAPR__MASK)
-static INLINE uint32_t
-nv50_tic_swizzle(uint32_t tc, unsigned swz, boolean tex_int)
+static inline uint32_t
+nv50_tic_swizzle(uint32_t tc, unsigned swz, bool tex_int)
{
switch (swz) {
case PIPE_SWIZZLE_RED:
{
uint32_t flags = 0;
- if (res->target == PIPE_TEXTURE_RECT || res->target == PIPE_BUFFER)
+ if (templ->target == PIPE_TEXTURE_RECT || templ->target == PIPE_BUFFER)
flags |= NV50_TEXVIEW_SCALED_COORDS;
- return nv50_create_texture_view(pipe, res, templ, flags, res->target);
+ return nv50_create_texture_view(pipe, res, templ, flags, templ->target);
}
struct pipe_sampler_view *
uint32_t flags,
enum pipe_texture_target target)
{
+ const uint32_t class_3d = nouveau_context(pipe)->screen->class_3d;
const struct util_format_description *desc;
uint64_t addr;
uint32_t *tic;
uint32_t depth;
struct nv50_tic_entry *view;
struct nv50_miptree *mt = nv50_miptree(texture);
- boolean tex_int;
+ bool tex_int;
view = MALLOC_STRUCT(nv50_tic_entry);
if (!view)
addr = mt->base.address;
- if (mt->base.base.target == PIPE_TEXTURE_1D_ARRAY ||
- mt->base.base.target == PIPE_TEXTURE_2D_ARRAY) {
+ depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
+
+ if (mt->base.base.array_size > 1) {
+ /* there doesn't seem to be a base layer field in TIC */
addr += view->pipe.u.tex.first_layer * mt->layer_stride;
depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
- } else {
- depth = mt->base.base.depth0;
}
tic[2] = 0x10001000 | NV50_TIC_2_NO_BORDER;
tic[2] |= NV50_TIC_2_LINEAR | NV50_TIC_2_TARGET_RECT;
tic[3] = mt->level[0].pitch;
tic[4] = mt->base.base.width0;
- tic[5] = (1 << 16) | mt->base.base.height0;
+ tic[5] = (1 << 16) | (mt->base.base.height0);
}
tic[6] =
tic[7] = 0;
break;
default:
NOUVEAU_ERR("invalid texture target: %d\n", mt->base.base.target);
- return FALSE;
+ return false;
}
tic[3] = (flags & NV50_TEXVIEW_FILTER_MSAA8) ? 0x20000000 : 0x00300000;
tic[5] = (mt->base.base.height0 << mt->ms_y) & 0xffff;
tic[5] |= depth << 16;
- tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ if (class_3d > NV50_3D_CLASS)
+ tic[5] |= mt->base.base.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
+ else
+ tic[5] |= view->pipe.u.tex.last_level << NV50_TIC_5_LAST_LEVEL__SHIFT;
tic[6] = (mt->ms_x > 1) ? 0x88000000 : 0x03000000; /* sampling points */
- tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
+ if (class_3d > NV50_3D_CLASS)
+ tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
+ else
+ tic[7] = 0;
if (unlikely(!(tic[2] & NV50_TIC_2_NORMALIZED_COORDS)))
if (mt->base.base.last_level)
return &view->pipe;
}
-static boolean
+static void
+nv50_update_tic(struct nv50_context *nv50, struct nv50_tic_entry *tic,
+ struct nv04_resource *res)
+{
+ uint64_t address = res->address;
+ if (res->base.target != PIPE_BUFFER)
+ return;
+ address += tic->pipe.u.buf.first_element *
+ util_format_get_blocksize(tic->pipe.format);
+ if (tic->tic[1] == (uint32_t)address &&
+ (tic->tic[2] & 0xff) == address >> 32)
+ return;
+
+ nv50_screen_tic_unlock(nv50->screen, tic);
+ tic->id = -1;
+ tic->tic[1] = address;
+ tic->tic[2] &= 0xffffff00;
+ tic->tic[2] |= address >> 32;
+}
+
+static bool
nv50_validate_tic(struct nv50_context *nv50, int s)
{
struct nouveau_pushbuf *push = nv50->base.pushbuf;
struct nouveau_bo *txc = nv50->screen->txc;
unsigned i;
- boolean need_flush = FALSE;
+ bool need_flush = false;
assert(nv50->num_textures[s] <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nv50->num_textures[s]; ++i) {
continue;
}
res = &nv50_miptree(tic->pipe.texture)->base;
+ nv50_update_tic(nv50, tic, res);
if (tic->id < 0) {
tic->id = nv50_screen_tic_alloc(nv50->screen, tic);
BEGIN_NI04(push, NV50_2D(SIFC_DATA), 8);
PUSH_DATAp(push, &tic->tic[0], 8);
- need_flush = TRUE;
+ need_flush = true;
} else
if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1);
BEGIN_NV04(push, NV50_3D(BIND_TIC(s)), 1);
PUSH_DATA (push, (i << 1) | 0);
}
+ if (nv50->num_textures[s]) {
+ BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
+ PUSH_DATA (push, ((NV50_CB_AUX_TEX_MS_OFFSET + 16 * s * 2 * 4) << (8 - 2)) | NV50_CB_AUX);
+ BEGIN_NI04(push, NV50_3D(CB_DATA(0)), nv50->num_textures[s] * 2);
+ for (i = 0; i < nv50->num_textures[s]; i++) {
+ struct nv50_tic_entry *tic = nv50_tic_entry(nv50->textures[s][i]);
+ struct nv50_miptree *res;
+
+ if (!tic) {
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 0);
+ continue;
+ }
+ res = nv50_miptree(tic->pipe.texture);
+ PUSH_DATA (push, res->ms_x);
+ PUSH_DATA (push, res->ms_y);
+ }
+ }
nv50->state.num_textures[s] = nv50->num_textures[s];
return need_flush;
void nv50_validate_textures(struct nv50_context *nv50)
{
- boolean need_flush;
+ bool need_flush;
need_flush = nv50_validate_tic(nv50, 0);
+ need_flush |= nv50_validate_tic(nv50, 1);
need_flush |= nv50_validate_tic(nv50, 2);
if (need_flush) {
}
}
-static boolean
+static bool
nv50_validate_tsc(struct nv50_context *nv50, int s)
{
struct nouveau_pushbuf *push = nv50->base.pushbuf;
unsigned i;
- boolean need_flush = FALSE;
+ bool need_flush = false;
assert(nv50->num_samplers[s] <= PIPE_MAX_SAMPLERS);
for (i = 0; i < nv50->num_samplers[s]; ++i) {
nv50_sifc_linear_u8(&nv50->base, nv50->screen->txc,
65536 + tsc->id * 32,
NOUVEAU_BO_VRAM, 32, tsc->tsc);
- need_flush = TRUE;
+ need_flush = true;
}
nv50->screen->tsc.lock[tsc->id / 32] |= 1 << (tsc->id % 32);
void nv50_validate_samplers(struct nv50_context *nv50)
{
- boolean need_flush;
+ bool need_flush;
need_flush = nv50_validate_tsc(nv50, 0);
+ need_flush |= nv50_validate_tsc(nv50, 1);
need_flush |= nv50_validate_tsc(nv50, 2);
if (need_flush) {
PUSH_DATA (nv50->base.pushbuf, 0);
}
}
+
+/* There can be up to 4 different MS levels (1, 2, 4, 8). To simplify the
+ * shader logic, allow each one to take up 8 offsets.
+ */
+#define COMBINE(x, y) x, y
+#define DUMMY 0, 0
+static const uint32_t msaa_sample_xy_offsets[] = {
+ /* MS1 */
+ COMBINE(0, 0),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS2 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS4 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ COMBINE(0, 1),
+ COMBINE(1, 1),
+ DUMMY,
+ DUMMY,
+ DUMMY,
+ DUMMY,
+
+ /* MS8 */
+ COMBINE(0, 0),
+ COMBINE(1, 0),
+ COMBINE(0, 1),
+ COMBINE(1, 1),
+ COMBINE(2, 0),
+ COMBINE(3, 0),
+ COMBINE(2, 1),
+ COMBINE(3, 1),
+};
+
+void nv50_upload_ms_info(struct nouveau_pushbuf *push)
+{
+ BEGIN_NV04(push, NV50_3D(CB_ADDR), 1);
+ PUSH_DATA (push, (NV50_CB_AUX_MS_OFFSET << (8 - 2)) | NV50_CB_AUX);
+ BEGIN_NI04(push, NV50_3D(CB_DATA(0)), Elements(msaa_sample_xy_offsets));
+ PUSH_DATAp(push, msaa_sample_xy_offsets, Elements(msaa_sample_xy_offsets));
+}
projects / mesa.git / blobdiff