nvc0: reduce likelihood of collision for real buffers on Fermi

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_compute.c

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
index 83768a2f6f4b834715d2f1e3b82e7a933ca56e01..c07f186af5ceefb697a02340287863a9ffc6088f 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_compute.c
@@ -90,13 +90,13 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
    BEGIN_NVC0(push, NVC0_COMPUTE(WARP_TEMP_ALLOC), 1);
    PUSH_DATA (push, 0);
    BEGIN_NVC0(push, NVC0_COMPUTE(LOCAL_BASE), 1);
-   PUSH_DATA (push, 1 << 24);
+   PUSH_DATA (push, 0xff << 24);
 
    /* shared memory setup */
    BEGIN_NVC0(push, NVC0_COMPUTE(CACHE_SPLIT), 1);
    PUSH_DATA (push, NVC0_COMPUTE_CACHE_SPLIT_48K_SHARED_16K_L1);
    BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_BASE), 1);
-   PUSH_DATA (push, 2 << 24);
+   PUSH_DATA (push, 0xfe << 24);
    BEGIN_NVC0(push, NVC0_COMPUTE(SHARED_SIZE), 1);
    PUSH_DATA (push, 0);
 
@@ -105,7 +105,17 @@ nvc0_screen_compute_setup(struct nvc0_screen *screen,
    PUSH_DATAh(push, screen->text->offset);
    PUSH_DATA (push, screen->text->offset);
 
-   /* TODO: textures & samplers */
+   /* textures */
+   BEGIN_NVC0(push, NVC0_COMPUTE(TIC_ADDRESS_HIGH), 3);
+   PUSH_DATAh(push, screen->txc->offset);
+   PUSH_DATA (push, screen->txc->offset);
+   PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
+
+   /* samplers */
+   BEGIN_NVC0(push, NVC0_COMPUTE(TSC_ADDRESS_HIGH), 3);
+   PUSH_DATAh(push, screen->txc->offset + 65536);
+   PUSH_DATA (push, screen->txc->offset + 65536);
+   PUSH_DATA (push, NVC0_TSC_MAX_ENTRIES - 1);
 
    return 0;
 }
@@ -138,6 +148,26 @@ nvc0_compute_validate_program(struct nvc0_context *nvc0)
    return false;
 }
 
+static void
+nvc0_compute_validate_samplers(struct nvc0_context *nvc0)
+{
+   bool need_flush = nvc0_validate_tsc(nvc0, 5);
+   if (need_flush) {
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TSC_FLUSH), 1);
+      PUSH_DATA (nvc0->base.pushbuf, 0);
+   }
+}
+
+static void
+nvc0_compute_validate_textures(struct nvc0_context *nvc0)
+{
+   bool need_flush = nvc0_validate_tic(nvc0, 5);
+   if (need_flush) {
+      BEGIN_NVC0(nvc0->base.pushbuf, NVC0_COMPUTE(TIC_FLUSH), 1);
+      PUSH_DATA (nvc0->base.pushbuf, 0);
+   }
+}
+
 static void
 nvc0_compute_validate_constbufs(struct nvc0_context *nvc0)
 {
@@ -255,8 +285,12 @@ nvc0_compute_state_validate(struct nvc0_context *nvc0)
       nvc0_compute_validate_driverconst(nvc0);
    if (nvc0->dirty_cp & NVC0_NEW_CP_BUFFERS)
       nvc0_compute_validate_buffers(nvc0);
+   if (nvc0->dirty_cp & NVC0_NEW_CP_TEXTURES)
+      nvc0_compute_validate_textures(nvc0);
+   if (nvc0->dirty_cp & NVC0_NEW_CP_SAMPLERS)
+      nvc0_compute_validate_samplers(nvc0);
 
-   /* TODO: textures, samplers, surfaces, global memory buffers */
+   /* TODO: surfaces, global memory buffers */
 
    nvc0_bufctx_fence(nvc0, nvc0->bufctx_cp, false);
 
@@ -326,14 +360,6 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
    BEGIN_NVC0(push, NVC0_COMPUTE(CP_GPR_ALLOC), 1);
    PUSH_DATA (push, cp->num_gprs);
 
-   /* grid/block setup */
-   BEGIN_NVC0(push, NVC0_COMPUTE(GRIDDIM_YX), 2);
-   PUSH_DATA (push, (info->grid[1] << 16) | info->grid[0]);
-   PUSH_DATA (push, info->grid[2]);
-   BEGIN_NVC0(push, NVC0_COMPUTE(BLOCKDIM_YX), 2);
-   PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
-   PUSH_DATA (push, info->block[2]);
-
    /* launch preliminary setup */
    BEGIN_NVC0(push, NVC0_COMPUTE(GRIDID), 1);
    PUSH_DATA (push, 0x1);
@@ -342,17 +368,39 @@ nvc0_launch_grid(struct pipe_context *pipe, const struct pipe_grid_info *info)
    BEGIN_NVC0(push, NVC0_COMPUTE(FLUSH), 1);
    PUSH_DATA (push, NVC0_COMPUTE_FLUSH_GLOBAL | NVC0_COMPUTE_FLUSH_UNK8);
 
-   /* kernel launching */
-   BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_BEGIN), 1);
-   PUSH_DATA (push, 0);
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x0a08), 1);
-   PUSH_DATA (push, 0);
-   BEGIN_NVC0(push, NVC0_COMPUTE(LAUNCH), 1);
-   PUSH_DATA (push, 0x1000);
-   BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_END), 1);
-   PUSH_DATA (push, 0);
-   BEGIN_NVC0(push, SUBC_COMPUTE(0x0360), 1);
-   PUSH_DATA (push, 0x1);
+   /* block setup */
+   BEGIN_NVC0(push, NVC0_COMPUTE(BLOCKDIM_YX), 2);
+   PUSH_DATA (push, (info->block[1] << 16) | info->block[0]);
+   PUSH_DATA (push, info->block[2]);
+
+   if (unlikely(info->indirect)) {
+      struct nv04_resource *res = nv04_resource(info->indirect);
+      uint32_t offset = res->offset + info->indirect_offset;
+      unsigned macro = NVC0_COMPUTE_MACRO_LAUNCH_GRID_INDIRECT;
+
+      nouveau_pushbuf_space(push, 16, 0, 1);
+      PUSH_REFN(push, res->bo, NOUVEAU_BO_RD | res->domain);
+      PUSH_DATA(push, NVC0_FIFO_PKHDR_1I(1, macro, 3));
+      nouveau_pushbuf_data(push, res->bo, offset,
+                           NVC0_IB_ENTRY_1_NO_PREFETCH | 3 * 4);
+   } else {
+      /* grid setup */
+      BEGIN_NVC0(push, NVC0_COMPUTE(GRIDDIM_YX), 2);
+      PUSH_DATA (push, (info->grid[1] << 16) | info->grid[0]);
+      PUSH_DATA (push, info->grid[2]);
+
+      /* kernel launching */
+      BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_BEGIN), 1);
+      PUSH_DATA (push, 0);
+      BEGIN_NVC0(push, SUBC_COMPUTE(0x0a08), 1);
+      PUSH_DATA (push, 0);
+      BEGIN_NVC0(push, NVC0_COMPUTE(LAUNCH), 1);
+      PUSH_DATA (push, 0x1000);
+      BEGIN_NVC0(push, NVC0_COMPUTE(COMPUTE_END), 1);
+      PUSH_DATA (push, 0);
+      BEGIN_NVC0(push, SUBC_COMPUTE(0x0360), 1);
+      PUSH_DATA (push, 0x1);
+   }
 
    /* Invalidate all 3D constbufs because they are aliased with COMPUTE. */
    nvc0->dirty |= NVC0_NEW_CONSTBUF;