gallium: add PIPE_CAP_TGSI_ATOMINC_WRAP to indicate support

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_context.h

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
index 77237a3c0a327ed2b3207b2e07010feecb4c8b2d..4cfd207d4c0473b13a52c8522f890723909d9ab0 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_context.h
@@ -138,7 +138,9 @@
 #define NVC0_CB_AUX_SAMPLE_INFO     0x1a0 /* FP */
 /* 256 bytes, though only 64 bytes used before GM200 */
 #define NVC0_CB_AUX_SAMPLE_SIZE     (8 * 2 * 4 * 4)
-/* draw parameters (index bais, base instance, drawid) */
+/* draw parameters (index bias, base instance, drawid)
+ * be sure to update the indirect draw macros in com9097.mme when changing this
+ */
 #define NVC0_CB_AUX_DRAW_INFO       0x1a0 /* VP */
 /* 32 user buffers, at 4 32-bits integers each */
 #define NVC0_CB_AUX_BUF_INFO(i)     0x2a0 + (i) * 4 * 4
@@ -146,7 +148,9 @@
 /* 8 surfaces, at 16 32-bits integers each */
 #define NVC0_CB_AUX_SU_INFO(i)      0x4a0 + (i) * 16 * 4
 #define NVC0_CB_AUX_SU_SIZE         (NVC0_MAX_IMAGES * 16 * 4)
-/* 1 64-bits address and 1 32-bits sequence */
+/* 1 64-bits address and 1 32-bits sequence
+ * be sure to update the shaders in nvc0_query_hw_sm.c when changing this
+ */
 #define NVC0_CB_AUX_MP_INFO         0x6a0
 #define NVC0_CB_AUX_MP_SIZE         3 * 4
 /* 512 64-byte blocks for bindless image handles */
@@ -278,6 +282,8 @@ struct nvc0_context {
    uint16_t images_valid[6];
 
    struct util_dynarray global_residents;
+
+   uint64_t compute_invocations;
 };
 
 static inline struct nvc0_context *
@@ -361,6 +367,7 @@ bool nve4_validate_tsc(struct nvc0_context *nvc0, int s);
 void nvc0_validate_suf(struct nvc0_context *nvc0, int s);
 void nvc0_validate_textures(struct nvc0_context *);
 void nvc0_validate_samplers(struct nvc0_context *);
+void nvc0_upload_tsc0(struct nvc0_context *);
 void nve4_set_tex_handles(struct nvc0_context *);
 void nvc0_validate_surfaces(struct nvc0_context *);
 void nve4_set_surface_info(struct nouveau_pushbuf *,
@@ -429,6 +436,7 @@ nvc0_video_buffer_create(struct pipe_context *pipe,
 
 /* nvc0_push.c */
 void nvc0_push_vbo(struct nvc0_context *, const struct pipe_draw_info *);
+void nvc0_push_vbo_indirect(struct nvc0_context *, const struct pipe_draw_info *);
 
 /* nve4_compute.c */
 void nve4_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
@@ -436,5 +444,7 @@ void nve4_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 /* nvc0_compute.c */
 void nvc0_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
 void nvc0_compute_validate_globals(struct nvc0_context *);
+void nvc0_update_compute_invocations_counter(struct nvc0_context *nvc0,
+                                             const struct pipe_grid_info *info);
 
 #endif