#define NVC0_NEW_3D_TESSFACTOR (1 << 25)
#define NVC0_NEW_3D_BUFFERS (1 << 26)
#define NVC0_NEW_3D_DRIVERCONST (1 << 27)
+#define NVC0_NEW_3D_WINDOW_RECTS (1 << 28)
#define NVC0_NEW_CP_PROGRAM (1 << 0)
#define NVC0_NEW_CP_SURFACES (1 << 1)
#define NVC0_BIND_M2MF 0
#define NVC0_BIND_FENCE 1
+/* 6 user uniform buffers, at 64K each */
+#define NVC0_CB_USR_INFO(s) (s << 16)
+#define NVC0_CB_USR_SIZE (6 << 16)
+/* 6 driver constbuts, at 2K each */
+#define NVC0_CB_AUX_INFO(s) NVC0_CB_USR_SIZE + (s << 11)
+#define NVC0_CB_AUX_SIZE (6 << 11)
+/* XXX: Figure out what this UNK data is. */
+#define NVC0_CB_AUX_UNK_INFO 0x000
+#define NVC0_CB_AUX_UNK_SIZE (8 * 4)
+/* 32 textures handles, at 1 32-bits integer each */
+#define NVC0_CB_AUX_TEX_INFO(i) 0x020 + (i) * 4
+#define NVC0_CB_AUX_TEX_SIZE (32 * 4)
+/* 8 sets of 32-bits coordinate offsets */
+#define NVC0_CB_AUX_MS_INFO 0x0a0
+#define NVC0_CB_AUX_MS_SIZE (8 * 2 * 4)
+/* block/grid size, at 3 32-bits integers each, gridid and work_dim */
+#define NVC0_CB_AUX_GRID_INFO(i) 0x0e0 + (i) * 4 /* CP */
+#define NVC0_CB_AUX_GRID_SIZE (8 * 4)
+/* 8 user clip planes, at 4 32-bits floats each */
+#define NVC0_CB_AUX_UCP_INFO 0x100
+#define NVC0_CB_AUX_UCP_SIZE (PIPE_MAX_CLIP_PLANES * 4 * 4)
+/* 13 ubos, at 4 32-bits integer each */
+#define NVC0_CB_AUX_UBO_INFO(i) 0x100 + (i) * 4 * 4 /* CP */
+#define NVC0_CB_AUX_UBO_SIZE ((NVC0_MAX_PIPE_CONSTBUFS - 1) * 4 * 4)
+/* 8 sets of 32-bits integer pairs sample offsets */
+#define NVC0_CB_AUX_SAMPLE_INFO 0x180 /* FP */
+#define NVC0_CB_AUX_SAMPLE_SIZE (8 * 4 * 2)
+/* draw parameters (index bais, base instance, drawid) */
+#define NVC0_CB_AUX_DRAW_INFO 0x180 /* VP */
+/* 32 user buffers, at 4 32-bits integers each */
+#define NVC0_CB_AUX_BUF_INFO(i) 0x200 + (i) * 4 * 4
+#define NVC0_CB_AUX_BUF_SIZE (NVC0_MAX_BUFFERS * 4 * 4)
+/* 8 surfaces, at 16 32-bits integers each */
+#define NVC0_CB_AUX_SU_INFO(i) 0x400 + (i) * 16 * 4
+#define NVC0_CB_AUX_SU_SIZE (NVC0_MAX_IMAGES * 16 * 4)
+/* 1 64-bits address and 1 32-bits sequence */
+#define NVC0_CB_AUX_MP_INFO 0x600
+#define NVC0_CB_AUX_MP_SIZE 3 * 4
+/* 4 32-bits floats for the vertex runout, put at the end */
+#define NVC0_CB_AUX_RUNOUT_INFO NVC0_CB_USR_SIZE + NVC0_CB_AUX_SIZE
struct nvc0_blitctx;
uint32_t textures_coherent[6];
struct nv50_tsc_entry *samplers[6][PIPE_MAX_SAMPLERS];
unsigned num_samplers[6];
- uint16_t samplers_dirty[6];
+ uint32_t samplers_dirty[6];
bool seamless_cube_map;
uint32_t tex_handles[6][PIPE_MAX_SAMPLERS]; /* for nve4 */
struct pipe_viewport_state viewports[NVC0_MAX_VIEWPORTS];
unsigned viewports_dirty;
struct pipe_clip_state clip;
+ struct nvc0_window_rect_stateobj window_rect;
unsigned sample_mask;
unsigned min_samples;
uint32_t buffers_dirty[6];
uint32_t buffers_valid[6];
+ struct pipe_image_view images[6][NVC0_MAX_IMAGES];
+ uint16_t images_dirty[6];
+ uint16_t images_valid[6];
+
struct util_dynarray global_residents;
};
void nvc0_tevlprog_validate(struct nvc0_context *);
void nvc0_gmtyprog_validate(struct nvc0_context *);
void nvc0_fragprog_validate(struct nvc0_context *);
+void nvc0_compprog_validate(struct nvc0_context *);
void nvc0_tfb_validate(struct nvc0_context *);
extern void nvc0_init_state_functions(struct nvc0_context *);
/* nvc0_state_validate.c */
-void nvc0_validate_global_residents(struct nvc0_context *,
- struct nouveau_bufctx *, int bin);
-bool nvc0_state_validate(struct nvc0_context *, uint32_t state_mask);
+struct nvc0_state_validate {
+ void (*func)(struct nvc0_context *);
+ uint32_t states;
+};
+
+bool nvc0_state_validate(struct nvc0_context *, uint32_t,
+ struct nvc0_state_validate *, int, uint32_t *,
+ struct nouveau_bufctx *);
+bool nvc0_state_validate_3d(struct nvc0_context *, uint32_t);
/* nvc0_surface.c */
extern void nvc0_clear(struct pipe_context *, unsigned buffers,
bool nvc0_validate_tic(struct nvc0_context *nvc0, int s);
bool nvc0_validate_tsc(struct nvc0_context *nvc0, int s);
bool nve4_validate_tsc(struct nvc0_context *nvc0, int s);
+void nvc0_validate_suf(struct nvc0_context *nvc0, int s);
void nvc0_validate_textures(struct nvc0_context *);
void nvc0_validate_samplers(struct nvc0_context *);
void nve4_set_tex_handles(struct nvc0_context *);
void nvc0_validate_surfaces(struct nvc0_context *);
-void nve4_set_surface_info(struct nouveau_pushbuf *, struct pipe_surface *,
- struct nvc0_screen *);
+void nve4_set_surface_info(struct nouveau_pushbuf *, struct pipe_image_view *,
+ struct nvc0_context *);
+void nvc0_mark_image_range_valid(const struct pipe_image_view *);
+void nvc0_update_tic(struct nvc0_context *, struct nv50_tic_entry *,
+ struct nv04_resource *);
struct pipe_sampler_view *
nvc0_create_texture_view(struct pipe_context *,
/* nvc0_compute.c */
void nvc0_launch_grid(struct pipe_context *, const struct pipe_grid_info *);
+void nvc0_compute_validate_globals(struct nvc0_context *);
#endif