#include "pipe/p_defines.h"
+#include "compiler/nir/nir.h"
#include "tgsi/tgsi_ureg.h"
#include "nvc0/nvc0_context.h"
{
unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
- tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
-
if (info->numPatchConstants)
opcs = 8 + info->numPatchConstants * 4;
static int
nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
{
- tep->tp.input_patch_size = ~0;
-
tep->hdr[0] = 0x20061 | (3 << 10);
tep->hdr[4] = 0xff000;
return tfb;
}
-#ifdef DEBUG
+#ifndef NDEBUG
static void
nvc0_program_dump(struct nvc0_program *prog)
{
unsigned pos;
if (prog->type != PIPE_SHADER_COMPUTE) {
+ _debug_printf("dumping HDR for type %i\n", prog->type);
for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
- debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
+ _debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
}
- debug_printf("shader binary code (0x%x bytes):", prog->code_size);
+ _debug_printf("shader binary code (0x%x bytes):", prog->code_size);
for (pos = 0; pos < prog->code_size / 4; ++pos) {
if ((pos % 8) == 0)
- debug_printf("\n");
- debug_printf("%08x ", prog->code[pos]);
+ _debug_printf("\n");
+ _debug_printf("%08x ", prog->code[pos]);
}
- debug_printf("\n");
+ _debug_printf("\n");
}
#endif
info->type = prog->type;
info->target = chipset;
- info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
- info->bin.source = (void *)prog->pipe.tokens;
-#ifdef DEBUG
+ info->bin.sourceRep = prog->pipe.type;
+ switch (prog->pipe.type) {
+ case PIPE_SHADER_IR_TGSI:
+ info->bin.source = (void *)prog->pipe.tokens;
+ break;
+ case PIPE_SHADER_IR_NIR:
+ info->bin.source = (void *)nir_shader_clone(NULL, prog->pipe.ir.nir);
+ break;
+ default:
+ assert(!"unsupported IR!");
+ free(info);
+ return false;
+ }
+
+#ifndef NDEBUG
info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
prog->num_gprs, info->bin.instructions,
info->bin.codeSize);
-#ifdef DEBUG
+#ifndef NDEBUG
if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
nvc0_program_dump(prog);
#endif
out:
+ if (info->bin.sourceRep == PIPE_SHADER_IR_NIR)
+ ralloc_free((void *)info->bin.source);
FREE(info);
return !ret;
}
NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
return false;
}
- nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- if (screen->compute) {
- nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- }
/* Re-upload the builtin function into the new code segment. */
nvc0_program_library_upload(nvc0);
nvc0_program_upload_code(nvc0, prog);
-#ifdef DEBUG
+#ifndef NDEBUG
if (debug_get_bool_option("NV50_PROG_DEBUG", false))
nvc0_program_dump(prog);
#endif