nouveau: flip DEBUG -> !NDEBUG

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_program.c

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index 46a15d76df006f8163456079433dce6e83ea9454..32487248c7aee7549b19d3ee3b37e264195f3b41 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -22,6 +22,7 @@
 
 #include "pipe/p_defines.h"
 
+#include "compiler/nir/nir.h"
 #include "tgsi/tgsi_ureg.h"
 
 #include "nvc0/nvc0_context.h"
@@ -134,10 +135,20 @@ nvc0_fp_assign_output_slots(struct nv50_ir_prog_info *info)
    unsigned count = info->prop.fp.numColourResults * 4;
    unsigned i, c;
 
+   /* Compute the relative position of each color output, since skipped MRT
+    * positions will not have registers allocated to them.
+    */
+   unsigned colors[8] = {0};
+   for (i = 0; i < info->numOutputs; ++i)
+      if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
+         colors[info->out[i].si] = 1;
+   for (i = 0, c = 0; i < 8; i++)
+      if (colors[i])
+         colors[i] = c++;
    for (i = 0; i < info->numOutputs; ++i)
       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
          for (c = 0; c < 4; ++c)
-            info->out[i].slot[c] = info->out[i].si * 4 + c;
+            info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
 
    if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
       info->out[info->io.sampleMask].slot[0] = count++;
@@ -332,8 +343,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 {
    unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
 
-   tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
-
    if (info->numPatchConstants)
       opcs = 8 + info->numPatchConstants * 4;
 
@@ -363,8 +372,6 @@ nvc0_tcp_gen_header(struct nvc0_program *tcp, struct nv50_ir_prog_info *info)
 static int
 nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
 {
-   tep->tp.input_patch_size = ~0;
-
    tep->hdr[0] = 0x20061 | (3 << 10);
    tep->hdr[4] = 0xff000;
 
@@ -471,10 +478,13 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nv50_ir_prog_info *info)
          }
       }
    }
+   /* GM20x+ needs TGSI_SEMANTIC_POSITION to access sample locations */
+   if (info->prop.fp.readsSampleLocations && info->target >= NVISA_GM200_CHIPSET)
+      fp->hdr[5] |= 0x30000000;
 
    for (i = 0; i < info->numOutputs; ++i) {
       if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
-         fp->hdr[18] |= 0xf << info->out[i].slot[0];
+         fp->hdr[18] |= 0xf << (4 * info->out[i].si);
    }
 
    /* There are no "regular" attachments, but the shader still needs to be
@@ -534,13 +544,14 @@ nvc0_program_create_tfb_state(const struct nv50_ir_prog_info *info,
    return tfb;
 }
 
-#ifdef DEBUG
+#ifndef NDEBUG
 static void
 nvc0_program_dump(struct nvc0_program *prog)
 {
    unsigned pos;
 
    if (prog->type != PIPE_SHADER_COMPUTE) {
+      debug_printf("dumping HDR for type %i\n", prog->type);
       for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
          debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
                       pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
@@ -568,10 +579,22 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
 
    info->type = prog->type;
    info->target = chipset;
-   info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
-   info->bin.source = (void *)prog->pipe.tokens;
 
-#ifdef DEBUG
+   info->bin.sourceRep = prog->pipe.type;
+   switch (prog->pipe.type) {
+   case PIPE_SHADER_IR_TGSI:
+      info->bin.source = (void *)prog->pipe.tokens;
+      break;
+   case PIPE_SHADER_IR_NIR:
+      info->bin.source = (void *)nir_shader_clone(NULL, prog->pipe.ir.nir);
+      break;
+   default:
+      assert(!"unsupported IR!");
+      free(info);
+      return false;
+   }
+
+#ifndef NDEBUG
    info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
    info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
    info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
@@ -592,6 +615,7 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
    if (info->target >= NVISA_GK104_CHIPSET) {
       info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
       info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
+      info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
    }
 
    if (prog->type == PIPE_SHADER_COMPUTE) {
@@ -690,12 +714,14 @@ nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
                       prog->num_gprs, info->bin.instructions,
                       info->bin.codeSize);
 
-#ifdef DEBUG
+#ifndef NDEBUG
    if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
       nvc0_program_dump(prog);
 #endif
 
 out:
+   if (info->bin.sourceRep == PIPE_SHADER_IR_NIR)
+      ralloc_free((void *)info->bin.source);
    FREE(info);
    return !ret;
 }
@@ -817,16 +843,6 @@ nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
             NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
             return false;
          }
-         nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
-         BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
-                      NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
-                      screen->text);
-         if (screen->compute) {
-            nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEXT);
-            BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT,
-                         NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
-                         screen->text);
-         }
 
          /* Re-upload the builtin function into the new code segment. */
          nvc0_program_library_upload(nvc0);
@@ -864,7 +880,7 @@ nvc0_program_upload(struct nvc0_context *nvc0, struct nvc0_program *prog)
 
    nvc0_program_upload_code(nvc0, prog);
 
-#ifdef DEBUG
+#ifndef NDEBUG
    if (debug_get_bool_option("NV50_PROG_DEBUG", false))
       nvc0_program_dump(prog);
 #endif