#include "pipe/p_defines.h"
+#include "compiler/nir/nir.h"
#include "tgsi/tgsi_ureg.h"
#include "nvc0/nvc0_context.h"
unsigned count = info->prop.fp.numColourResults * 4;
unsigned i, c;
+ /* Compute the relative position of each color output, since skipped MRT
+ * positions will not have registers allocated to them.
+ */
+ unsigned colors[8] = {0};
+ for (i = 0; i < info->numOutputs; ++i)
+ if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
+ colors[info->out[i].si] = 1;
+ for (i = 0, c = 0; i < 8; i++)
+ if (colors[i])
+ colors[i] = c++;
for (i = 0; i < info->numOutputs; ++i)
if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
for (c = 0; c < 4; ++c)
- info->out[i].slot[c] = info->out[i].si * 4 + c;
+ info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
info->out[info->io.sampleMask].slot[0] = count++;
{
unsigned opcs = 6; /* output patch constants (at least the TessFactors) */
- tcp->tp.input_patch_size = info->prop.tp.inputPatchSize;
-
if (info->numPatchConstants)
opcs = 8 + info->numPatchConstants * 4;
static int
nvc0_tep_gen_header(struct nvc0_program *tep, struct nv50_ir_prog_info *info)
{
- tep->tp.input_patch_size = ~0;
-
tep->hdr[0] = 0x20061 | (3 << 10);
tep->hdr[4] = 0xff000;
}
}
}
+ /* GM20x+ needs TGSI_SEMANTIC_POSITION to access sample locations */
+ if (info->prop.fp.readsSampleLocations && info->target >= NVISA_GM200_CHIPSET)
+ fp->hdr[5] |= 0x30000000;
for (i = 0; i < info->numOutputs; ++i) {
if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
- fp->hdr[18] |= 0xf << info->out[i].slot[0];
+ fp->hdr[18] |= 0xf << (4 * info->out[i].si);
}
/* There are no "regular" attachments, but the shader still needs to be
fp->fp.early_z = info->prop.fp.earlyFragTests;
fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
+ fp->fp.reads_framebuffer = info->prop.fp.readsFramebuffer;
+ fp->fp.post_depth_coverage = info->prop.fp.postDepthCoverage;
+
+ /* Mark position xy and layer as read */
+ if (fp->fp.reads_framebuffer)
+ fp->hdr[5] |= 0x32000000;
return 0;
}
for (i = 0; i < pso->num_outputs; ++i) {
unsigned s = pso->output[i].start_component;
unsigned p = pso->output[i].dst_offset;
+ const unsigned r = pso->output[i].register_index;
b = pso->output[i].output_buffer;
+ if (r >= info->numOutputs)
+ continue;
+
for (c = 0; c < pso->output[i].num_components; ++c)
- tfb->varying_index[b][p++] =
- info->out[pso->output[i].register_index].slot[s + c];
+ tfb->varying_index[b][p++] = info->out[r].slot[s + c];
tfb->varying_count[b] = MAX2(tfb->varying_count[b], p);
tfb->stream[b] = pso->output[i].stream;
return tfb;
}
-#ifdef DEBUG
+#ifndef NDEBUG
static void
nvc0_program_dump(struct nvc0_program *prog)
{
unsigned pos;
if (prog->type != PIPE_SHADER_COMPUTE) {
+ debug_printf("dumping HDR for type %i\n", prog->type);
for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
info->type = prog->type;
info->target = chipset;
- info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
- info->bin.source = (void *)prog->pipe.tokens;
+ info->bin.sourceRep = prog->pipe.type;
+ switch (prog->pipe.type) {
+ case PIPE_SHADER_IR_TGSI:
+ info->bin.source = (void *)prog->pipe.tokens;
+ break;
+ case PIPE_SHADER_IR_NIR:
+ info->bin.source = (void *)nir_shader_clone(NULL, prog->pipe.ir.nir);
+ break;
+ default:
+ assert(!"unsupported IR!");
+ free(info);
+ return false;
+ }
+
+#ifndef NDEBUG
+ info->target = debug_get_num_option("NV50_PROG_CHIPSET", chipset);
+ info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
+ info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
+ info->omitLineNum = debug_get_num_option("NV50_PROG_DEBUG_OMIT_LINENUM", 0);
+#else
+ info->optLevel = 3;
+#endif
+
+ info->bin.smemSize = prog->cp.smem_size;
info->io.genUserClip = prog->vp.num_ucps;
info->io.auxCBSlot = 15;
info->io.msInfoCBSlot = 15;
info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
- if (chipset >= NVISA_GK104_CHIPSET) {
+ if (info->target >= NVISA_GK104_CHIPSET) {
info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
+ info->io.fbtexBindBase = NVC0_CB_AUX_FB_TEX_INFO;
+ info->io.bindlessBase = NVC0_CB_AUX_BINDLESS_INFO(0);
}
if (prog->type == PIPE_SHADER_COMPUTE) {
- if (chipset >= NVISA_GK104_CHIPSET) {
+ if (info->target >= NVISA_GK104_CHIPSET) {
info->io.auxCBSlot = 7;
info->io.msInfoCBSlot = 7;
info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
info->assignSlots = nvc0_program_assign_varying_slots;
-#ifdef DEBUG
- info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
- info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
-#else
- info->optLevel = 3;
-#endif
-
ret = nv50_ir_generate_code(info);
if (ret) {
NOUVEAU_ERR("shader translation failed: %i\n", ret);
prog->relocs = info->bin.relocData;
prog->fixups = info->bin.fixupData;
prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
+ prog->cp.smem_size = info->bin.smemSize;
prog->num_barriers = info->numBarriers;
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
&prog->pipe.stream_output);
pipe_debug_message(debug, SHADER_INFO,
- "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
- prog->type, info->bin.tlsSpace, prog->num_gprs,
- info->bin.instructions, info->bin.codeSize);
+ "type: %d, local: %d, shared: %d, gpr: %d, inst: %d, bytes: %d",
+ prog->type, info->bin.tlsSpace, info->bin.smemSize,
+ prog->num_gprs, info->bin.instructions,
+ info->bin.codeSize);
+
+#ifndef NDEBUG
+ if (debug_get_option("NV50_PROG_CHIPSET", NULL) && info->dbgFlags)
+ nvc0_program_dump(prog);
+#endif
out:
+ if (info->bin.sourceRep == PIPE_SHADER_IR_NIR)
+ ralloc_free((void *)info->bin.source);
FREE(info);
return !ret;
}
NOUVEAU_ERR("Error allocating TEXT area: %d\n", ret);
return false;
}
- nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_3d, 3D_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- if (screen->compute) {
- nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_TEXT);
- BCTX_REFN_bo(nvc0->bufctx_cp, CP_TEXT,
- NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_RD,
- screen->text);
- }
/* Re-upload the builtin function into the new code segment. */
nvc0_program_library_upload(nvc0);
nvc0_program_upload_code(nvc0, prog);
-#ifdef DEBUG
+#ifndef NDEBUG
if (debug_get_bool_option("NV50_PROG_DEBUG", false))
nvc0_program_dump(prog);
#endif
projects / mesa.git / blobdiff