#include "pipe/p_defines.h"
+#include "tgsi/tgsi_ureg.h"
+
#include "nvc0/nvc0_context.h"
#include "codegen/nv50_ir_driver.h"
* 124 scalar varying values.
*/
static uint32_t
-nvc0_shader_input_address(unsigned sn, unsigned si, unsigned ubase)
+nvc0_shader_input_address(unsigned sn, unsigned si)
{
switch (sn) {
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
- case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
+ case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
case TGSI_SEMANTIC_INSTANCEID: return 0x2f8;
case TGSI_SEMANTIC_VERTEXID: return 0x2fc;
case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
- case TGSI_SEMANTIC_FACE: return 0x3fc;
default:
assert(!"invalid TGSI input semantic");
return ~0;
}
static uint32_t
-nvc0_shader_output_address(unsigned sn, unsigned si, unsigned ubase)
+nvc0_shader_output_address(unsigned sn, unsigned si)
{
switch (sn) {
case TGSI_SEMANTIC_TESSOUTER: return 0x000 + si * 0x4;
case TGSI_SEMANTIC_VIEWPORT_INDEX:return 0x068;
case TGSI_SEMANTIC_PSIZE: return 0x06c;
case TGSI_SEMANTIC_POSITION: return 0x070;
- case TGSI_SEMANTIC_GENERIC: return ubase + si * 0x10;
+ case TGSI_SEMANTIC_GENERIC: return 0x080 + si * 0x10;
case TGSI_SEMANTIC_FOG: return 0x2e8;
case TGSI_SEMANTIC_COLOR: return 0x280 + si * 0x10;
case TGSI_SEMANTIC_BCOLOR: return 0x2a0 + si * 0x10;
case TGSI_SEMANTIC_CLIPDIST: return 0x2c0 + si * 0x10;
case TGSI_SEMANTIC_CLIPVERTEX: return 0x270;
case TGSI_SEMANTIC_TEXCOORD: return 0x300 + si * 0x10;
+ /* case TGSI_SEMANTIC_VIEWPORT_MASK: return 0x3a0; */
case TGSI_SEMANTIC_EDGEFLAG: return ~0;
default:
assert(!"invalid TGSI output semantic");
case TGSI_SEMANTIC_VERTEXID:
info->in[i].mask = 0x1;
info->in[i].slot[0] =
- nvc0_shader_input_address(info->in[i].sn, 0, 0) / 4;
+ nvc0_shader_input_address(info->in[i].sn, 0) / 4;
continue;
default:
break;
static int
nvc0_sp_assign_input_slots(struct nv50_ir_prog_info *info)
{
- unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numInputs; ++i) {
- offset = nvc0_shader_input_address(info->in[i].sn,
- info->in[i].si, ubase);
+ offset = nvc0_shader_input_address(info->in[i].sn, info->in[i].si);
for (c = 0; c < 4; ++c)
info->in[i].slot[c] = (offset + c * 0x4) / 4;
static int
nvc0_sp_assign_output_slots(struct nv50_ir_prog_info *info)
{
- unsigned ubase = MAX2(0x80, 0x20 + info->numPatchConstants * 0x10);
unsigned offset;
unsigned i, c;
for (i = 0; i < info->numOutputs; ++i) {
- offset = nvc0_shader_output_address(info->out[i].sn,
- info->out[i].si, ubase);
+ offset = nvc0_shader_output_address(info->out[i].sn, info->out[i].si);
for (c = 0; c < 4; ++c)
info->out[i].slot[c] = (offset + c * 0x4) / 4;
}
}
- vp->vp.clip_enable = info->io.clipDistanceMask;
- for (i = 0; i < 8; ++i)
- if (info->io.cullDistanceMask & (1 << i))
- vp->vp.clip_mode |= 1 << (i * 4);
+ vp->vp.clip_enable = (1 << info->io.clipDistances) - 1;
+ vp->vp.cull_enable =
+ ((1 << info->io.cullDistances) - 1) << info->io.clipDistances;
+ for (i = 0; i < info->io.cullDistances; ++i)
+ vp->vp.clip_mode |= 1 << ((info->io.clipDistances + i) * 4);
if (info->io.genUserClip < 0)
vp->vp.num_ucps = PIPE_MAX_CLIP_PLANES + 1; /* prevent rebuilding */
vp->hdr[0] = 0x20061 | (1 << 10);
vp->hdr[4] = 0xff000;
- vp->hdr[18] = info->io.clipDistanceMask;
-
return nvc0_vtgp_gen_header(vp, info);
}
break;
case PIPE_PRIM_TRIANGLES:
tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_TRIANGLES;
- if (info->prop.tp.winding > 0)
- tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
break;
case PIPE_PRIM_QUADS:
tp->tp.tess_mode = NVC0_3D_TESS_MODE_PRIM_QUADS;
tp->tp.tess_mode = ~0;
return;
}
- if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS)
- tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
+
+ /* It seems like lines want the "CW" bit to indicate they're connected, and
+ * spit out errors in dmesg when the "CONNECTED" bit is set.
+ */
+ if (info->prop.tp.outputPrim != PIPE_PRIM_POINTS) {
+ if (info->prop.tp.domain == PIPE_PRIM_LINES)
+ tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
+ else
+ tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CONNECTED;
+ }
+
+ /* Winding only matters for triangles/quads, not lines. */
+ if (info->prop.tp.domain != PIPE_PRIM_LINES &&
+ info->prop.tp.outputPrim != PIPE_PRIM_POINTS &&
+ info->prop.tp.winding > 0)
+ tp->tp.tess_mode |= NVC0_3D_TESS_MODE_CW;
switch (info->prop.tp.partitioning) {
case PIPE_TESS_SPACING_EQUAL:
break;
}
- gp->hdr[4] = MIN2(info->prop.gp.maxVertices, 1024);
+ gp->hdr[4] = CLAMP(info->prop.gp.maxVertices, 1, 1024);
return nvc0_vtgp_gen_header(gp, info);
}
for (i = 0; i < info->numInputs; ++i) {
m = nvc0_hdr_interp_mode(&info->in[i]);
+ if (info->in[i].sn == TGSI_SEMANTIC_COLOR) {
+ fp->fp.colors |= 1 << info->in[i].si;
+ if (info->in[i].sc)
+ fp->fp.color_interp[info->in[i].si] = m | (info->in[i].mask << 4);
+ }
for (c = 0; c < 4; ++c) {
if (!(info->in[i].mask & (1 << c)))
continue;
for (i = 0; i < info->numOutputs; ++i) {
if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
- fp->hdr[18] |= info->out[i].mask << info->out[i].slot[0];
+ fp->hdr[18] |= 0xf << info->out[i].slot[0];
}
+ /* There are no "regular" attachments, but the shader still needs to be
+ * executed. It seems like it wants to think that it has some color
+ * outputs in order to actually run.
+ */
+ if (info->prop.fp.numColourResults == 0 && !info->prop.fp.writesDepth)
+ fp->hdr[18] |= 0xf;
+
fp->fp.early_z = info->prop.fp.earlyFragTests;
+ fp->fp.sample_mask_in = info->prop.fp.usesSampleMaskIn;
return 0;
}
unsigned pos;
if (prog->type != PIPE_SHADER_COMPUTE) {
- for (pos = 0; pos < sizeof(prog->hdr) / sizeof(prog->hdr[0]); ++pos)
+ for (pos = 0; pos < ARRAY_SIZE(prog->hdr); ++pos)
debug_printf("HDR[%02"PRIxPTR"] = 0x%08x\n",
pos * sizeof(prog->hdr[0]), prog->hdr[pos]);
}
#endif
bool
-nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset)
+nvc0_program_translate(struct nvc0_program *prog, uint16_t chipset,
+ struct pipe_debug_callback *debug)
{
struct nv50_ir_prog_info *info;
int ret;
info->bin.source = (void *)prog->pipe.tokens;
info->io.genUserClip = prog->vp.num_ucps;
- info->io.ucpBase = 256;
- info->io.ucpCBSlot = 15;
- info->io.sampleInterp = prog->fp.sample_interp;
+ info->io.auxCBSlot = 15;
+ info->io.msInfoCBSlot = 15;
+ info->io.ucpBase = NVC0_CB_AUX_UCP_INFO;
+ info->io.drawInfoBase = NVC0_CB_AUX_DRAW_INFO;
+ info->io.msInfoBase = NVC0_CB_AUX_MS_INFO;
+ info->io.bufInfoBase = NVC0_CB_AUX_BUF_INFO(0);
+ info->io.suInfoBase = NVC0_CB_AUX_SU_INFO(0);
+ if (chipset >= NVISA_GK104_CHIPSET) {
+ info->io.texBindBase = NVC0_CB_AUX_TEX_INFO(0);
+ }
if (prog->type == PIPE_SHADER_COMPUTE) {
if (chipset >= NVISA_GK104_CHIPSET) {
- info->io.resInfoCBSlot = 0;
- info->io.texBindBase = NVE4_CP_INPUT_TEX(0);
- info->io.suInfoBase = NVE4_CP_INPUT_SUF(0);
- info->prop.cp.gridInfoBase = NVE4_CP_INPUT_GRID_INFO(0);
+ info->io.auxCBSlot = 7;
+ info->io.msInfoCBSlot = 7;
+ info->io.uboInfoBase = NVC0_CB_AUX_UBO_INFO(0);
}
- info->io.msInfoCBSlot = 0;
- info->io.msInfoBase = NVE4_CP_INPUT_MS_OFFSETS;
+ info->prop.cp.gridInfoBase = NVC0_CB_AUX_GRID_INFO(0);
} else {
- if (chipset >= NVISA_GK104_CHIPSET) {
- info->io.texBindBase = 0x20;
- info->io.suInfoBase = 0; /* TODO */
- }
- info->io.resInfoCBSlot = 15;
- info->io.sampleInfoBase = 256 + 128;
- info->io.msInfoCBSlot = 15;
- info->io.msInfoBase = 0; /* TODO */
+ info->io.sampleInfoBase = NVC0_CB_AUX_SAMPLE_INFO;
}
info->assignSlots = nvc0_program_assign_varying_slots;
prog->immd_data = info->immd.buf;
prog->immd_size = info->immd.bufSize;
prog->relocs = info->bin.relocData;
+ prog->fixups = info->bin.fixupData;
prog->num_gprs = MAX2(4, (info->bin.maxGPR + 1));
prog->num_barriers = info->numBarriers;
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
+ prog->vp.need_draw_parameters = info->prop.vp.usesDrawParameters;
if (info->io.edgeFlagOut < PIPE_MAX_ATTRIBS)
info->out[info->io.edgeFlagOut].mask = 0; /* for headergen */
}
*/
if (info->io.globalAccess)
+ prog->hdr[0] |= 1 << 26;
+ if (info->io.globalAccess & 0x2)
prog->hdr[0] |= 1 << 16;
if (info->io.fp64)
prog->hdr[0] |= 1 << 27;
prog->tfb = nvc0_program_create_tfb_state(info,
&prog->pipe.stream_output);
+ pipe_debug_message(debug, SHADER_INFO,
+ "type: %d, local: %d, gpr: %d, inst: %d, bytes: %d",
+ prog->type, info->bin.tlsSpace, prog->num_gprs,
+ info->bin.instructions, info->bin.codeSize);
+
out:
FREE(info);
return !ret;
if (prog->relocs)
nv50_ir_relocate_code(prog->relocs, prog->code, code_pos, lib_pos, 0);
+ if (prog->fixups) {
+ nv50_ir_apply_fixups(prog->fixups, prog->code,
+ prog->fp.force_persample_interp,
+ prog->fp.flatshade,
+ 0 /* alphatest */);
+ for (int i = 0; i < 2; i++) {
+ unsigned mask = prog->fp.color_interp[i] >> 4;
+ unsigned interp = prog->fp.color_interp[i] & 3;
+ if (!mask)
+ continue;
+ prog->hdr[14] &= ~(0xff << (8 * i));
+ if (prog->fp.flatshade)
+ interp = NVC0_INTERP_FLAT;
+ for (int c = 0; c < 4; c++)
+ if (mask & (1 << c))
+ prog->hdr[14] |= interp << (2 * (4 * i + c));
+ }
+ }
#ifdef DEBUG
if (debug_get_bool_option("NV50_PROG_DEBUG", false))
FREE(prog->code); /* may be 0 for hardcoded shaders */
FREE(prog->immd_data);
FREE(prog->relocs);
+ FREE(prog->fixups);
if (prog->type == PIPE_SHADER_COMPUTE && prog->cp.syms)
FREE(prog->cp.syms);
if (prog->tfb) {
return prog->code_base + base + syms[i].offset;
return prog->code_base; /* no symbols or symbol not found */
}
+
+void
+nvc0_program_init_tcp_empty(struct nvc0_context *nvc0)
+{
+ struct ureg_program *ureg;
+
+ ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
+ if (!ureg)
+ return;
+
+ ureg_property(ureg, TGSI_PROPERTY_TCS_VERTICES_OUT, 1);
+ ureg_END(ureg);
+
+ nvc0->tcp_empty = ureg_create_shader_and_destroy(ureg, &nvc0->base.pipe);
+}
projects / mesa.git / blobdiff