#include "nvc0/nvc0_context.h"
#include "nvc0/nvc0_query_hw.h"
-
-#include "nv_object.xml.h"
-#include "nvc0/nve4_compute.xml.h"
-#include "nvc0/nvc0_compute.xml.h"
-
-#define NVC0_HW_QUERY_STATE_READY 0
-#define NVC0_HW_QUERY_STATE_ACTIVE 1
-#define NVC0_HW_QUERY_STATE_ENDED 2
-#define NVC0_HW_QUERY_STATE_FLUSHED 3
+#include "nvc0/nvc0_query_hw_metric.h"
+#include "nvc0/nvc0_query_hw_sm.h"
#define NVC0_HW_QUERY_ALLOC_SPACE 256
-/* === PERFORMANCE MONITORING COUNTERS for NVE4+ === */
-
-/* Code to read out MP counters: They are accessible via mmio, too, but let's
- * just avoid mapping registers in userspace. We'd have to know which MPs are
- * enabled/present, too, and that information is not presently exposed.
- * We could add a kernel interface for it, but reading the counters like this
- * has the advantage of being async (if get_result isn't called immediately).
- */
-static const uint64_t nve4_read_hw_sm_counters_code[] =
-{
- /* sched 0x20 0x20 0x20 0x20 0x20 0x20 0x20
- * mov b32 $r8 $tidx
- * mov b32 $r12 $physid
- * mov b32 $r0 $pm0
- * mov b32 $r1 $pm1
- * mov b32 $r2 $pm2
- * mov b32 $r3 $pm3
- * mov b32 $r4 $pm4
- * sched 0x20 0x20 0x23 0x04 0x20 0x04 0x2b
- * mov b32 $r5 $pm5
- * mov b32 $r6 $pm6
- * mov b32 $r7 $pm7
- * set $p0 0x1 eq u32 $r8 0x0
- * mov b32 $r10 c0[0x0]
- * ext u32 $r8 $r12 0x414
- * mov b32 $r11 c0[0x4]
- * sched 0x04 0x2e 0x04 0x20 0x20 0x28 0x04
- * ext u32 $r9 $r12 0x208
- * (not $p0) exit
- * set $p1 0x1 eq u32 $r9 0x0
- * mul $r8 u32 $r8 u32 96
- * mul $r12 u32 $r9 u32 16
- * mul $r13 u32 $r9 u32 4
- * add b32 $r9 $r8 $r13
- * sched 0x28 0x04 0x2c 0x04 0x2c 0x04 0x2c
- * add b32 $r8 $r8 $r12
- * mov b32 $r12 $r10
- * add b32 $r10 $c $r10 $r8
- * mov b32 $r13 $r11
- * add b32 $r11 $r11 0x0 $c
- * add b32 $r12 $c $r12 $r9
- * st b128 wt g[$r10d] $r0q
- * sched 0x4 0x2c 0x20 0x04 0x2e 0x00 0x00
- * mov b32 $r0 c0[0x8]
- * add b32 $r13 $r13 0x0 $c
- * $p1 st b128 wt g[$r12d+0x40] $r4q
- * st b32 wt g[$r12d+0x50] $r0
- * exit */
- 0x2202020202020207ULL,
- 0x2c00000084021c04ULL,
- 0x2c0000000c031c04ULL,
- 0x2c00000010001c04ULL,
- 0x2c00000014005c04ULL,
- 0x2c00000018009c04ULL,
- 0x2c0000001c00dc04ULL,
- 0x2c00000020011c04ULL,
- 0x22b0420042320207ULL,
- 0x2c00000024015c04ULL,
- 0x2c00000028019c04ULL,
- 0x2c0000002c01dc04ULL,
- 0x190e0000fc81dc03ULL,
- 0x2800400000029de4ULL,
- 0x7000c01050c21c03ULL,
- 0x280040001002dde4ULL,
- 0x204282020042e047ULL,
- 0x7000c00820c25c03ULL,
- 0x80000000000021e7ULL,
- 0x190e0000fc93dc03ULL,
- 0x1000000180821c02ULL,
- 0x1000000040931c02ULL,
- 0x1000000010935c02ULL,
- 0x4800000034825c03ULL,
- 0x22c042c042c04287ULL,
- 0x4800000030821c03ULL,
- 0x2800000028031de4ULL,
- 0x4801000020a29c03ULL,
- 0x280000002c035de4ULL,
- 0x0800000000b2dc42ULL,
- 0x4801000024c31c03ULL,
- 0x9400000000a01fc5ULL,
- 0x200002e04202c047ULL,
- 0x2800400020001de4ULL,
- 0x0800000000d35c42ULL,
- 0x9400000100c107c5ULL,
- 0x9400000140c01f85ULL,
- 0x8000000000001de7ULL
-};
-
-/* For simplicity, we will allocate as many group slots as we allocate counter
- * slots. This means that a single counter which wants to source from 2 groups
- * will have to be declared as using 2 counter slots. This shouldn't really be
- * a problem because such queries don't make much sense ... (unless someone is
- * really creative).
- */
-struct nvc0_mp_counter_cfg
-{
- uint32_t func : 16; /* mask or 4-bit logic op (depending on mode) */
- uint32_t mode : 4; /* LOGOP,B6,LOGOP_B6(_PULSE) */
- uint32_t num_src : 3; /* number of sources (1 - 6, only for NVC0:NVE4) */
- uint32_t sig_dom : 1; /* if 0, MP_PM_A (per warp-sched), if 1, MP_PM_B */
- uint32_t sig_sel : 8; /* signal group */
- uint64_t src_sel; /* signal selection for up to 6 sources (48 bit) */
-};
-
-#define NVC0_COUNTER_OPn_SUM 0
-#define NVC0_COUNTER_OPn_OR 1
-#define NVC0_COUNTER_OPn_AND 2
-#define NVC0_COUNTER_OP2_REL_SUM_MM 3 /* (sum(ctr0) - sum(ctr1)) / sum(ctr0) */
-#define NVC0_COUNTER_OP2_DIV_SUM_M0 4 /* sum(ctr0) / ctr1 of MP[0]) */
-#define NVC0_COUNTER_OP2_AVG_DIV_MM 5 /* avg(ctr0 / ctr1) */
-#define NVC0_COUNTER_OP2_AVG_DIV_M0 6 /* avg(ctr0) / ctr1 of MP[0]) */
-
-struct nvc0_hw_sm_query_cfg
-{
- struct nvc0_mp_counter_cfg ctr[4];
- uint8_t num_counters;
- uint8_t op;
- uint8_t norm[2]; /* normalization num,denom */
-};
-
-#define _Q1A(n, f, m, g, s, nu, dn) [NVE4_HW_SM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
-#define _Q1B(n, f, m, g, s, nu, dn) [NVE4_HW_SM_QUERY_##n] = { { { f, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g, s }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { nu, dn } }
-#define _M2A(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_HW_SM_QUERY_METRIC_##n] = { { \
- { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
- { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g1, s1 }, \
- {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
-#define _M2B(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_HW_SM_QUERY_METRIC_##n] = { { \
- { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g0, s0 }, \
- { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
- {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
-#define _M2AB(n, f0, m0, g0, s0, f1, m1, g1, s1, o, nu, dn) [NVE4_HW_SM_QUERY_METRIC_##n] = { { \
- { f0, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m0, 0, 0, NVE4_COMPUTE_MP_PM_A_SIGSEL_##g0, s0 }, \
- { f1, NVE4_COMPUTE_MP_PM_FUNC_MODE_##m1, 0, 1, NVE4_COMPUTE_MP_PM_B_SIGSEL_##g1, s1 }, \
- {}, {}, }, 2, NVC0_COUNTER_OP2_##o, { nu, dn } }
-
-/* NOTES:
- * active_warps: bit 0 alternates btw 0 and 1 for odd nr of warps
- * inst_executed etc.: we only count a single warp scheduler
- * metric-ipXc: we simply multiply by 4 to account for the 4 warp schedulers;
- * this is inaccurate !
- */
-static const struct nvc0_hw_sm_query_cfg nve4_hw_sm_queries[] =
-{
- _Q1B(ACTIVE_CYCLES, 0x0001, B6, WARP, 0x00000000, 1, 1),
- _Q1B(ACTIVE_WARPS, 0x003f, B6, WARP, 0x31483104, 2, 1),
- _Q1A(ATOM_COUNT, 0x0001, B6, BRANCH, 0x00000000, 1, 1),
- _Q1A(BRANCH, 0x0001, B6, BRANCH, 0x0000000c, 1, 1),
- _Q1A(DIVERGENT_BRANCH, 0x0001, B6, BRANCH, 0x00000010, 1, 1),
- _Q1A(GLD_REQUEST, 0x0001, B6, LDST, 0x00000010, 1, 1),
- _Q1B(GLD_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000010, 1, 1),
- _Q1B(GST_TRANSACTIONS, 0x0001, B6, MEM, 0x00000004, 1, 1),
- _Q1B(GST_MEM_DIV_REPLAY, 0x0001, B6, REPLAY, 0x00000014, 1, 1),
- _Q1A(GRED_COUNT, 0x0001, B6, BRANCH, 0x00000008, 1, 1),
- _Q1A(GST_REQUEST, 0x0001, B6, LDST, 0x00000014, 1, 1),
- _Q1A(INST_EXECUTED, 0x0003, B6, EXEC, 0x00000398, 1, 1),
- _Q1A(INST_ISSUED, 0x0003, B6, ISSUE, 0x00000104, 1, 1),
- _Q1A(INST_ISSUED1, 0x0001, B6, ISSUE, 0x00000004, 1, 1),
- _Q1A(INST_ISSUED2, 0x0001, B6, ISSUE, 0x00000008, 1, 1),
- _Q1B(L1_GLD_HIT, 0x0001, B6, L1, 0x00000010, 1, 1),
- _Q1B(L1_GLD_MISS, 0x0001, B6, L1, 0x00000014, 1, 1),
- _Q1B(L1_LOCAL_LD_HIT, 0x0001, B6, L1, 0x00000000, 1, 1),
- _Q1B(L1_LOCAL_LD_MISS, 0x0001, B6, L1, 0x00000004, 1, 1),
- _Q1B(L1_LOCAL_ST_HIT, 0x0001, B6, L1, 0x00000008, 1, 1),
- _Q1B(L1_LOCAL_ST_MISS, 0x0001, B6, L1, 0x0000000c, 1, 1),
- _Q1B(L1_SHARED_LD_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000008, 1, 1),
- _Q1B(L1_SHARED_ST_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x0000000c, 1, 1),
- _Q1A(LOCAL_LD, 0x0001, B6, LDST, 0x00000008, 1, 1),
- _Q1B(LOCAL_LD_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000000, 1, 1),
- _Q1A(LOCAL_ST, 0x0001, B6, LDST, 0x0000000c, 1, 1),
- _Q1B(LOCAL_ST_TRANSACTIONS, 0x0001, B6, TRANSACTION, 0x00000004, 1, 1),
- _Q1A(PROF_TRIGGER_0, 0x0001, B6, USER, 0x00000000, 1, 1),
- _Q1A(PROF_TRIGGER_1, 0x0001, B6, USER, 0x00000004, 1, 1),
- _Q1A(PROF_TRIGGER_2, 0x0001, B6, USER, 0x00000008, 1, 1),
- _Q1A(PROF_TRIGGER_3, 0x0001, B6, USER, 0x0000000c, 1, 1),
- _Q1A(PROF_TRIGGER_4, 0x0001, B6, USER, 0x00000010, 1, 1),
- _Q1A(PROF_TRIGGER_5, 0x0001, B6, USER, 0x00000014, 1, 1),
- _Q1A(PROF_TRIGGER_6, 0x0001, B6, USER, 0x00000018, 1, 1),
- _Q1A(PROF_TRIGGER_7, 0x0001, B6, USER, 0x0000001c, 1, 1),
- _Q1A(SHARED_LD, 0x0001, B6, LDST, 0x00000000, 1, 1),
- _Q1B(SHARED_LD_REPLAY, 0x0001, B6, REPLAY, 0x00000008, 1, 1),
- _Q1A(SHARED_ST, 0x0001, B6, LDST, 0x00000004, 1, 1),
- _Q1B(SHARED_ST_REPLAY, 0x0001, B6, REPLAY, 0x0000000c, 1, 1),
- _Q1B(SM_CTA_LAUNCHED, 0x0001, B6, WARP, 0x0000001c, 1, 1),
- _Q1A(THREADS_LAUNCHED, 0x003f, B6, LAUNCH, 0x398a4188, 1, 1),
- _Q1B(UNCACHED_GLD_TRANSACTIONS, 0x0001, B6, MEM, 0x00000000, 1, 1),
- _Q1A(WARPS_LAUNCHED, 0x0001, B6, LAUNCH, 0x00000004, 1, 1),
- _M2AB(IPC, 0x3, B6, EXEC, 0x398, 0xffff, LOGOP, WARP, 0x0, DIV_SUM_M0, 10, 1),
- _M2AB(IPAC, 0x3, B6, EXEC, 0x398, 0x1, B6, WARP, 0x0, AVG_DIV_MM, 10, 1),
- _M2A(IPEC, 0x3, B6, EXEC, 0x398, 0xe, LOGOP, EXEC, 0x398, AVG_DIV_MM, 10, 1),
- _M2A(INST_REPLAY_OHEAD, 0x3, B6, ISSUE, 0x104, 0x3, B6, EXEC, 0x398, REL_SUM_MM, 100, 1),
- _M2B(MP_OCCUPANCY, 0x3f, B6, WARP, 0x31483104, 0x01, B6, WARP, 0x0, AVG_DIV_MM, 200, 64),
- _M2B(MP_EFFICIENCY, 0x01, B6, WARP, 0x0, 0xffff, LOGOP, WARP, 0x0, AVG_DIV_M0, 100, 1),
-};
-
-#undef _Q1A
-#undef _Q1B
-#undef _M2A
-#undef _M2B
-
-/* === PERFORMANCE MONITORING COUNTERS for NVC0:NVE4 === */
-static const uint64_t nvc0_read_hw_sm_counters_code[] =
-{
- /* mov b32 $r8 $tidx
- * mov b32 $r9 $physid
- * mov b32 $r0 $pm0
- * mov b32 $r1 $pm1
- * mov b32 $r2 $pm2
- * mov b32 $r3 $pm3
- * mov b32 $r4 $pm4
- * mov b32 $r5 $pm5
- * mov b32 $r6 $pm6
- * mov b32 $r7 $pm7
- * set $p0 0x1 eq u32 $r8 0x0
- * mov b32 $r10 c0[0x0]
- * mov b32 $r11 c0[0x4]
- * ext u32 $r8 $r9 0x414
- * (not $p0) exit
- * mul $r8 u32 $r8 u32 36
- * add b32 $r10 $c $r10 $r8
- * add b32 $r11 $r11 0x0 $c
- * mov b32 $r8 c0[0x8]
- * st b128 wt g[$r10d+0x00] $r0q
- * st b128 wt g[$r10d+0x10] $r4q
- * st b32 wt g[$r10d+0x20] $r8
- * exit */
- 0x2c00000084021c04ULL,
- 0x2c0000000c025c04ULL,
- 0x2c00000010001c04ULL,
- 0x2c00000014005c04ULL,
- 0x2c00000018009c04ULL,
- 0x2c0000001c00dc04ULL,
- 0x2c00000020011c04ULL,
- 0x2c00000024015c04ULL,
- 0x2c00000028019c04ULL,
- 0x2c0000002c01dc04ULL,
- 0x190e0000fc81dc03ULL,
- 0x2800400000029de4ULL,
- 0x280040001002dde4ULL,
- 0x7000c01050921c03ULL,
- 0x80000000000021e7ULL,
- 0x1000000090821c02ULL,
- 0x4801000020a29c03ULL,
- 0x0800000000b2dc42ULL,
- 0x2800400020021de4ULL,
- 0x9400000000a01fc5ULL,
- 0x9400000040a11fc5ULL,
- 0x9400000080a21f85ULL,
- 0x8000000000001de7ULL
-};
-
-#define _Q(n, f, m, g, c, s0, s1, s2, s3, s4, s5) [NVC0_HW_SM_QUERY_##n] = { { { f, NVC0_COMPUTE_MP_PM_OP_MODE_##m, c, 0, g, s0|(s1 << 8)|(s2 << 16)|(s3 << 24)|(s4##ULL << 32)|(s5##ULL << 40) }, {}, {}, {} }, 1, NVC0_COUNTER_OPn_SUM, { 1, 1 } }
-
-static const struct nvc0_hw_sm_query_cfg nvc0_hw_sm_queries[] =
-{
- _Q(ACTIVE_CYCLES, 0xaaaa, LOGOP, 0x11, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(ACTIVE_WARPS, 0xaaaa, LOGOP, 0x24, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
- _Q(ATOM_COUNT, 0xaaaa, LOGOP, 0x63, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(BRANCH, 0xaaaa, LOGOP, 0x1a, 2, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00),
- _Q(DIVERGENT_BRANCH, 0xaaaa, LOGOP, 0x19, 2, 0x20, 0x31, 0x00, 0x00, 0x00, 0x00),
- _Q(GLD_REQUEST, 0xaaaa, LOGOP, 0x64, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(GRED_COUNT, 0xaaaa, LOGOP, 0x63, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(GST_REQUEST, 0xaaaa, LOGOP, 0x64, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(INST_EXECUTED, 0xaaaa, LOGOP, 0x2d, 3, 0x00, 0x11, 0x22, 0x00, 0x00, 0x00),
- _Q(INST_ISSUED1_0, 0xaaaa, LOGOP, 0x7e, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(INST_ISSUED1_1, 0xaaaa, LOGOP, 0x7e, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(INST_ISSUED2_0, 0xaaaa, LOGOP, 0x7e, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(INST_ISSUED2_1, 0xaaaa, LOGOP, 0x7e, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(LOCAL_LD, 0xaaaa, LOGOP, 0x64, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(LOCAL_ST, 0xaaaa, LOGOP, 0x64, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_0, 0xaaaa, LOGOP, 0x01, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_1, 0xaaaa, LOGOP, 0x01, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_2, 0xaaaa, LOGOP, 0x01, 1, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_3, 0xaaaa, LOGOP, 0x01, 1, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_4, 0xaaaa, LOGOP, 0x01, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_5, 0xaaaa, LOGOP, 0x01, 1, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_6, 0xaaaa, LOGOP, 0x01, 1, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(PROF_TRIGGER_7, 0xaaaa, LOGOP, 0x01, 1, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(SHARED_LD, 0xaaaa, LOGOP, 0x64, 1, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(SHARED_ST, 0xaaaa, LOGOP, 0x64, 1, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00),
- _Q(THREADS_LAUNCHED, 0xaaaa, LOGOP, 0x26, 6, 0x10, 0x21, 0x32, 0x43, 0x54, 0x65),
- _Q(TH_INST_EXECUTED_0, 0xaaaa, LOGOP, 0xa3, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
- _Q(TH_INST_EXECUTED_1, 0xaaaa, LOGOP, 0xa5, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
- _Q(TH_INST_EXECUTED_2, 0xaaaa, LOGOP, 0xa4, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
- _Q(TH_INST_EXECUTED_3, 0xaaaa, LOGOP, 0xa6, 6, 0x00, 0x11, 0x22, 0x33, 0x44, 0x55),
- _Q(WARPS_LAUNCHED, 0xaaaa, LOGOP, 0x26, 1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00),
-};
-
-#undef _Q
-
-static const struct nvc0_hw_sm_query_cfg *
-nvc0_hw_sm_query_get_cfg(struct nvc0_context *nvc0, struct nvc0_query *q)
-{
- struct nvc0_screen *screen = nvc0->screen;
-
- if (screen->base.class_3d >= NVE4_3D_CLASS)
- return &nve4_hw_sm_queries[q->type - PIPE_QUERY_DRIVER_SPECIFIC];
- return &nvc0_hw_sm_queries[q->type - NVC0_HW_SM_QUERY(0)];
-}
-
-static boolean
-nvc0_hw_sm_query_begin(struct nvc0_context *nvc0, struct nvc0_query *q)
-{
- struct nvc0_screen *screen = nvc0->screen;
- struct nouveau_pushbuf *push = nvc0->base.pushbuf;
- const bool is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS;
- struct nvc0_hw_query *hq = nvc0_hw_query(q);
- const struct nvc0_hw_sm_query_cfg *cfg;
- unsigned i, c;
- unsigned num_ab[2] = { 0, 0 };
-
- cfg = nvc0_hw_sm_query_get_cfg(nvc0, q);
-
- /* check if we have enough free counter slots */
- for (i = 0; i < cfg->num_counters; ++i)
- num_ab[cfg->ctr[i].sig_dom]++;
-
- if (screen->pm.num_hw_sm_active[0] + num_ab[0] > 4 ||
- screen->pm.num_hw_sm_active[1] + num_ab[1] > 4) {
- NOUVEAU_ERR("Not enough free MP counter slots !\n");
- return false;
- }
-
- assert(cfg->num_counters <= 4);
- PUSH_SPACE(push, 4 * 8 * (is_nve4 ? 1 : 6) + 6);
-
- if (!screen->pm.mp_counters_enabled) {
- screen->pm.mp_counters_enabled = true;
- BEGIN_NVC0(push, SUBC_SW(0x06ac), 1);
- PUSH_DATA (push, 0x1fcb);
- }
-
- /* set sequence field to 0 (used to check if result is available) */
- for (i = 0; i < screen->mp_count; ++i)
- hq->data[i * 10 + 10] = 0;
-
- for (i = 0; i < cfg->num_counters; ++i) {
- const unsigned d = cfg->ctr[i].sig_dom;
-
- if (!screen->pm.num_hw_sm_active[d]) {
- uint32_t m = (1 << 22) | (1 << (7 + (8 * !d)));
- if (screen->pm.num_hw_sm_active[!d])
- m |= 1 << (7 + (8 * d));
- BEGIN_NVC0(push, SUBC_SW(0x0600), 1);
- PUSH_DATA (push, m);
- }
- screen->pm.num_hw_sm_active[d]++;
-
- for (c = d * 4; c < (d * 4 + 4); ++c) {
- if (!screen->pm.mp_counter[c]) {
- hq->ctr[i] = c;
- screen->pm.mp_counter[c] = (struct pipe_query *)q;
- break;
- }
- }
- assert(c <= (d * 4 + 3)); /* must succeed, already checked for space */
-
- /* configure and reset the counter(s) */
- if (is_nve4) {
- if (d == 0)
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_A_SIGSEL(c & 3)), 1);
- else
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_B_SIGSEL(c & 3)), 1);
- PUSH_DATA (push, cfg->ctr[i].sig_sel);
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SRCSEL(c)), 1);
- PUSH_DATA (push, cfg->ctr[i].src_sel + 0x2108421 * (c & 3));
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 1);
- PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_SET(c)), 1);
- PUSH_DATA (push, 0);
- } else {
- unsigned s;
-
- for (s = 0; s < cfg->ctr[i].num_src; s++) {
- BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SIGSEL(s)), 1);
- PUSH_DATA (push, cfg->ctr[i].sig_sel);
- BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SRCSEL(s)), 1);
- PUSH_DATA (push, (cfg->ctr[i].src_sel >> (s * 8)) & 0xff);
- BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(s)), 1);
- PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
- BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_SET(s)), 1);
- PUSH_DATA (push, 0);
- }
- }
- }
- return true;
-}
-
-static void
-nvc0_hw_sm_query_end(struct nvc0_context *nvc0, struct nvc0_query *q)
-{
- struct nvc0_screen *screen = nvc0->screen;
- struct pipe_context *pipe = &nvc0->base.pipe;
- struct nouveau_pushbuf *push = nvc0->base.pushbuf;
- const bool is_nve4 = screen->base.class_3d >= NVE4_3D_CLASS;
- struct nvc0_hw_query *hq = nvc0_hw_query(q);
- uint32_t mask;
- uint32_t input[3];
- const uint block[3] = { 32, is_nve4 ? 4 : 1, 1 };
- const uint grid[3] = { screen->mp_count, 1, 1 };
- unsigned c;
- const struct nvc0_hw_sm_query_cfg *cfg;
-
- cfg = nvc0_hw_sm_query_get_cfg(nvc0, q);
-
- if (unlikely(!screen->pm.prog)) {
- struct nvc0_program *prog = CALLOC_STRUCT(nvc0_program);
- prog->type = PIPE_SHADER_COMPUTE;
- prog->translated = true;
- prog->num_gprs = 14;
- prog->parm_size = 12;
- if (is_nve4) {
- prog->code = (uint32_t *)nve4_read_hw_sm_counters_code;
- prog->code_size = sizeof(nve4_read_hw_sm_counters_code);
- } else {
- prog->code = (uint32_t *)nvc0_read_hw_sm_counters_code;
- prog->code_size = sizeof(nvc0_read_hw_sm_counters_code);
- }
- screen->pm.prog = prog;
- }
-
- /* disable all counting */
- PUSH_SPACE(push, 8);
- for (c = 0; c < 8; ++c)
- if (screen->pm.mp_counter[c]) {
- if (is_nve4) {
- IMMED_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(c)), 0);
- } else {
- IMMED_NVC0(push, NVC0_COMPUTE(MP_PM_OP(c)), 0);
- }
- }
- /* release counters for this query */
- for (c = 0; c < 8; ++c) {
- if (nvc0_query(screen->pm.mp_counter[c]) == q) {
- screen->pm.num_hw_sm_active[c / 4]--;
- screen->pm.mp_counter[c] = NULL;
- }
- }
-
- BCTX_REFN_bo(nvc0->bufctx_cp, CP_QUERY, NOUVEAU_BO_GART | NOUVEAU_BO_WR,
- hq->bo);
-
- PUSH_SPACE(push, 1);
- IMMED_NVC0(push, SUBC_COMPUTE(NV50_GRAPH_SERIALIZE), 0);
-
- pipe->bind_compute_state(pipe, screen->pm.prog);
- input[0] = (hq->bo->offset + hq->base_offset);
- input[1] = (hq->bo->offset + hq->base_offset) >> 32;
- input[2] = hq->sequence;
- pipe->launch_grid(pipe, block, grid, 0, input);
-
- nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_QUERY);
-
- /* re-activate other counters */
- PUSH_SPACE(push, 16);
- mask = 0;
- for (c = 0; c < 8; ++c) {
- unsigned i;
- q = nvc0_query(screen->pm.mp_counter[c]);
- if (!q)
- continue;
- cfg = nvc0_hw_sm_query_get_cfg(nvc0, q);
- for (i = 0; i < cfg->num_counters; ++i) {
- if (mask & (1 << hq->ctr[i]))
- break;
- mask |= 1 << hq->ctr[i];
- if (is_nve4) {
- BEGIN_NVC0(push, NVE4_COMPUTE(MP_PM_FUNC(hq->ctr[i])), 1);
- } else {
- BEGIN_NVC0(push, NVC0_COMPUTE(MP_PM_OP(hq->ctr[i])), 1);
- }
- PUSH_DATA (push, (cfg->ctr[i].func << 4) | cfg->ctr[i].mode);
- }
- }
-}
-
-static inline bool
-nvc0_hw_sm_query_read_data(uint32_t count[32][4],
- struct nvc0_context *nvc0, bool wait,
- struct nvc0_query *q,
- const struct nvc0_hw_sm_query_cfg *cfg,
- unsigned mp_count)
-{
- struct nvc0_hw_query *hq = nvc0_hw_query(q);
- unsigned p, c;
-
- for (p = 0; p < mp_count; ++p) {
- const unsigned b = (0x24 / 4) * p;
-
- for (c = 0; c < cfg->num_counters; ++c) {
- if (hq->data[b + 8] != hq->sequence) {
- if (!wait)
- return false;
- if (nouveau_bo_wait(hq->bo, NOUVEAU_BO_RD, nvc0->base.client))
- return false;
- }
- count[p][c] = hq->data[b + hq->ctr[c]];
- }
- }
- return true;
-}
-
-static inline bool
-nve4_hw_sm_query_read_data(uint32_t count[32][4],
- struct nvc0_context *nvc0, bool wait,
- struct nvc0_query *q,
- const struct nvc0_hw_sm_query_cfg *cfg,
- unsigned mp_count)
-{
- struct nvc0_hw_query *hq = nvc0_hw_query(q);
- unsigned p, c, d;
-
- for (p = 0; p < mp_count; ++p) {
- const unsigned b = (0x60 / 4) * p;
-
- for (c = 0; c < cfg->num_counters; ++c) {
- count[p][c] = 0;
- for (d = 0; d < ((hq->ctr[c] & ~3) ? 1 : 4); ++d) {
- if (hq->data[b + 20 + d] != hq->sequence) {
- if (!wait)
- return false;
- if (nouveau_bo_wait(hq->bo, NOUVEAU_BO_RD, nvc0->base.client))
- return false;
- }
- if (hq->ctr[c] & ~0x3)
- count[p][c] = hq->data[b + 16 + (hq->ctr[c] & 3)];
- else
- count[p][c] += hq->data[b + d * 4 + hq->ctr[c]];
- }
- }
- }
- return true;
-}
-
-/* Metric calculations:
- * sum(x) ... sum of x over all MPs
- * avg(x) ... average of x over all MPs
- *
- * IPC : sum(inst_executed) / clock
- * INST_REPLAY_OHEAD: (sum(inst_issued) - sum(inst_executed)) / sum(inst_issued)
- * MP_OCCUPANCY : avg((active_warps / 64) / active_cycles)
- * MP_EFFICIENCY : avg(active_cycles / clock)
- *
- * NOTE: Interpretation of IPC requires knowledge of MP count.
- */
-static boolean
-nvc0_hw_sm_query_result(struct nvc0_context *nvc0, struct nvc0_query *q,
- void *result, boolean wait)
-{
- uint32_t count[32][4];
- uint64_t value = 0;
- unsigned mp_count = MIN2(nvc0->screen->mp_count_compute, 32);
- unsigned p, c;
- const struct nvc0_hw_sm_query_cfg *cfg;
- bool ret;
-
- cfg = nvc0_hw_sm_query_get_cfg(nvc0, q);
-
- if (nvc0->screen->base.class_3d >= NVE4_3D_CLASS)
- ret = nve4_hw_sm_query_read_data(count, nvc0, wait, q, cfg, mp_count);
- else
- ret = nvc0_hw_sm_query_read_data(count, nvc0, wait, q, cfg, mp_count);
- if (!ret)
- return false;
-
- if (cfg->op == NVC0_COUNTER_OPn_SUM) {
- for (c = 0; c < cfg->num_counters; ++c)
- for (p = 0; p < mp_count; ++p)
- value += count[p][c];
- value = (value * cfg->norm[0]) / cfg->norm[1];
- } else
- if (cfg->op == NVC0_COUNTER_OPn_OR) {
- uint32_t v = 0;
- for (c = 0; c < cfg->num_counters; ++c)
- for (p = 0; p < mp_count; ++p)
- v |= count[p][c];
- value = ((uint64_t)v * cfg->norm[0]) / cfg->norm[1];
- } else
- if (cfg->op == NVC0_COUNTER_OPn_AND) {
- uint32_t v = ~0;
- for (c = 0; c < cfg->num_counters; ++c)
- for (p = 0; p < mp_count; ++p)
- v &= count[p][c];
- value = ((uint64_t)v * cfg->norm[0]) / cfg->norm[1];
- } else
- if (cfg->op == NVC0_COUNTER_OP2_REL_SUM_MM) {
- uint64_t v[2] = { 0, 0 };
- for (p = 0; p < mp_count; ++p) {
- v[0] += count[p][0];
- v[1] += count[p][1];
- }
- if (v[0])
- value = ((v[0] - v[1]) * cfg->norm[0]) / (v[0] * cfg->norm[1]);
- } else
- if (cfg->op == NVC0_COUNTER_OP2_DIV_SUM_M0) {
- for (p = 0; p < mp_count; ++p)
- value += count[p][0];
- if (count[0][1])
- value = (value * cfg->norm[0]) / (count[0][1] * cfg->norm[1]);
- else
- value = 0;
- } else
- if (cfg->op == NVC0_COUNTER_OP2_AVG_DIV_MM) {
- unsigned mp_used = 0;
- for (p = 0; p < mp_count; ++p, mp_used += !!count[p][0])
- if (count[p][1])
- value += (count[p][0] * cfg->norm[0]) / count[p][1];
- if (mp_used)
- value /= (uint64_t)mp_used * cfg->norm[1];
- } else
- if (cfg->op == NVC0_COUNTER_OP2_AVG_DIV_M0) {
- unsigned mp_used = 0;
- for (p = 0; p < mp_count; ++p, mp_used += !!count[p][0])
- value += count[p][0];
- if (count[0][1] && mp_used) {
- value *= cfg->norm[0];
- value /= (uint64_t)count[0][1] * mp_used * cfg->norm[1];
- } else {
- value = 0;
- }
- }
-
- *(uint64_t *)result = value;
- return true;
-}
-
-static bool
+bool
nvc0_hw_query_allocate(struct nvc0_context *nvc0, struct nvc0_query *q,
int size)
{
nvc0_hw_destroy_query(struct nvc0_context *nvc0, struct nvc0_query *q)
{
struct nvc0_hw_query *hq = nvc0_hw_query(q);
+
+ if (hq->funcs && hq->funcs->destroy_query) {
+ hq->funcs->destroy_query(nvc0, hq);
+ return;
+ }
+
nvc0_hw_query_allocate(nvc0, q, 0);
nouveau_fence_ref(NULL, &hq->fence);
FREE(hq);
}
-static boolean
+static void
+nvc0_hw_query_write_compute_invocations(struct nvc0_context *nvc0,
+ struct nvc0_hw_query *hq,
+ uint32_t offset)
+{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+
+ nouveau_pushbuf_space(push, 16, 0, 8);
+ PUSH_REFN(push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_WR);
+ BEGIN_1IC0(push, NVC0_3D(MACRO_COMPUTE_COUNTER_TO_QUERY), 4);
+ PUSH_DATA (push, nvc0->compute_invocations);
+ PUSH_DATAh(push, nvc0->compute_invocations);
+ PUSH_DATAh(push, hq->bo->offset + hq->offset + offset);
+ PUSH_DATA (push, hq->bo->offset + hq->offset + offset);
+}
+
+static bool
nvc0_hw_begin_query(struct nvc0_context *nvc0, struct nvc0_query *q)
{
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_hw_query *hq = nvc0_hw_query(q);
bool ret = true;
+ if (hq->funcs && hq->funcs->begin_query)
+ return hq->funcs->begin_query(nvc0, hq);
+
/* For occlusion queries we have to change the storage, because a previous
* query might set the initial render conition to false even *after* we re-
* initialized it to true.
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
- hq->nesting = nvc0->screen->num_occlusion_queries_active++;
- if (hq->nesting) {
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
+ if (nvc0->screen->num_occlusion_queries_active++) {
nvc0_hw_query_get(push, q, 0x10, 0x0100f002);
} else {
PUSH_SPACE(push, 3);
BEGIN_NVC0(push, NVC0_3D(COUNTER_RESET), 1);
PUSH_DATA (push, NVC0_3D_COUNTER_RESET_SAMPLECNT);
IMMED_NVC0(push, NVC0_3D(SAMPLECNT_ENABLE), 1);
+ /* Given that the counter is reset, the contents at 0x10 are
+ * equivalent to doing the query -- we would get hq->sequence as the
+ * payload and 0 as the reported value. This is already set up above
+ * as in the hq->rotate case.
+ */
}
break;
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
nvc0_hw_query_get(push, q, 0x10, 0x03005002 | (q->index << 5));
break;
+ case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
+ /* XXX: This get actually writes the number of overflowed streams */
+ nvc0_hw_query_get(push, q, 0x10, 0x0f005002);
+ break;
case PIPE_QUERY_TIME_ELAPSED:
nvc0_hw_query_get(push, q, 0x10, 0x00005002);
break;
nvc0_hw_query_get(push, q, 0xc0 + 0x70, 0x0980a002); /* ROP, PIXELS */
nvc0_hw_query_get(push, q, 0xc0 + 0x80, 0x0d808002); /* TCP, LAUNCHES */
nvc0_hw_query_get(push, q, 0xc0 + 0x90, 0x0e809002); /* TEP, LAUNCHES */
+ nvc0_hw_query_write_compute_invocations(nvc0, hq, 0xc0 + 0xa0);
break;
default:
- if ((q->type >= NVE4_HW_SM_QUERY(0) && q->type <= NVE4_HW_SM_QUERY_LAST) ||
- (q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST)) {
- ret = nvc0_hw_sm_query_begin(nvc0, q);
- }
break;
}
hq->state = NVC0_HW_QUERY_STATE_ACTIVE;
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_hw_query *hq = nvc0_hw_query(q);
+ if (hq->funcs && hq->funcs->end_query) {
+ hq->funcs->end_query(nvc0, hq);
+ return;
+ }
+
if (hq->state != NVC0_HW_QUERY_STATE_ACTIVE) {
/* some queries don't require 'begin' to be called (e.g. GPU_FINISHED) */
if (hq->rotate)
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
nvc0_hw_query_get(push, q, 0, 0x0100f002);
if (--nvc0->screen->num_occlusion_queries_active == 0) {
PUSH_SPACE(push, 1);
nvc0_hw_query_get(push, q, 0x10, 0x06805002 | (q->index << 5));
break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
- /* TODO: How do we sum over all streams for render condition ? */
- /* PRIMS_DROPPED doesn't write sequence, use a ZERO query to sync on */
nvc0_hw_query_get(push, q, 0x00, 0x03005002 | (q->index << 5));
- nvc0_hw_query_get(push, q, 0x20, 0x00005002);
+ break;
+ case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
+ /* XXX: This get actually writes the number of overflowed streams */
+ nvc0_hw_query_get(push, q, 0x00, 0x0f005002);
break;
case PIPE_QUERY_TIMESTAMP:
case PIPE_QUERY_TIME_ELAPSED:
nvc0_hw_query_get(push, q, 0x70, 0x0980a002); /* ROP, PIXELS */
nvc0_hw_query_get(push, q, 0x80, 0x0d808002); /* TCP, LAUNCHES */
nvc0_hw_query_get(push, q, 0x90, 0x0e809002); /* TEP, LAUNCHES */
+ nvc0_hw_query_write_compute_invocations(nvc0, hq, 0xa0);
break;
case PIPE_QUERY_TIMESTAMP_DISJOINT:
/* This query is not issued on GPU because disjoint is forced to false */
nvc0_hw_query_get(push, q, 0x00, 0x0d005002 | (q->index << 5));
break;
default:
- if ((q->type >= NVE4_HW_SM_QUERY(0) && q->type <= NVE4_HW_SM_QUERY_LAST) ||
- (q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST)) {
- nvc0_hw_sm_query_end(nvc0, q);
- }
break;
}
if (hq->is64bit)
nouveau_fence_ref(nvc0->screen->base.fence.current, &hq->fence);
}
-static boolean
+static bool
nvc0_hw_get_query_result(struct nvc0_context *nvc0, struct nvc0_query *q,
- boolean wait, union pipe_query_result *result)
+ bool wait, union pipe_query_result *result)
{
struct nvc0_hw_query *hq = nvc0_hw_query(q);
uint64_t *res64 = (uint64_t*)result;
uint64_t *data64 = (uint64_t *)hq->data;
unsigned i;
- if ((q->type >= NVE4_HW_SM_QUERY(0) && q->type <= NVE4_HW_SM_QUERY_LAST) ||
- (q->type >= NVC0_HW_SM_QUERY(0) && q->type <= NVC0_HW_SM_QUERY_LAST)) {
- return nvc0_hw_sm_query_result(nvc0, q, result, wait);
- }
+ if (hq->funcs && hq->funcs->get_query_result)
+ return hq->funcs->get_query_result(nvc0, hq, wait, result);
if (hq->state != NVC0_HW_QUERY_STATE_READY)
nvc0_hw_query_update(nvc0->screen->base.client, q);
res64[0] = hq->data[1] - hq->data[5];
break;
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
res8[0] = hq->data[1] != hq->data[5];
break;
case PIPE_QUERY_PRIMITIVES_GENERATED: /* u64 count, u64 time */
res64[1] = data64[2] - data64[6];
break;
case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+ case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
res8[0] = data64[0] != data64[2];
break;
case PIPE_QUERY_TIMESTAMP:
res64[0] = data64[1] - data64[3];
break;
case PIPE_QUERY_PIPELINE_STATISTICS:
- for (i = 0; i < 10; ++i)
+ for (i = 0; i < 11; ++i)
res64[i] = data64[i * 2] - data64[24 + i * 2];
break;
case NVC0_HW_QUERY_TFB_BUFFER_OFFSET:
return true;
}
+static void
+nvc0_hw_get_query_result_resource(struct nvc0_context *nvc0,
+ struct nvc0_query *q,
+ bool wait,
+ enum pipe_query_value_type result_type,
+ int index,
+ struct pipe_resource *resource,
+ unsigned offset)
+{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ struct nvc0_hw_query *hq = nvc0_hw_query(q);
+ struct nv04_resource *buf = nv04_resource(resource);
+ unsigned qoffset = 0, stride;
+
+ assert(!hq->funcs || !hq->funcs->get_query_result);
+
+ if (index == -1) {
+ /* TODO: Use a macro to write the availability of the query */
+ if (hq->state != NVC0_HW_QUERY_STATE_READY)
+ nvc0_hw_query_update(nvc0->screen->base.client, q);
+ uint32_t ready[2] = {hq->state == NVC0_HW_QUERY_STATE_READY};
+ nvc0->base.push_cb(&nvc0->base, buf, offset,
+ result_type >= PIPE_QUERY_TYPE_I64 ? 2 : 1,
+ ready);
+
+ util_range_add(&buf->valid_buffer_range, offset,
+ offset + (result_type >= PIPE_QUERY_TYPE_I64 ? 8 : 4));
+
+ nvc0_resource_validate(buf, NOUVEAU_BO_WR);
+
+ return;
+ }
+
+ /* If the fence guarding this query has not been emitted, that makes a lot
+ * of the following logic more complicated.
+ */
+ if (hq->is64bit && hq->fence->state < NOUVEAU_FENCE_STATE_EMITTED)
+ nouveau_fence_emit(hq->fence);
+
+ /* We either need to compute a 32- or 64-bit difference between 2 values,
+ * and then store the result as either a 32- or 64-bit value. As such let's
+ * treat all inputs as 64-bit (and just push an extra 0 for the 32-bit
+ * ones), and have one macro that clamps result to i32, u32, or just
+ * outputs the difference (no need to worry about 64-bit clamping).
+ */
+ if (hq->state != NVC0_HW_QUERY_STATE_READY)
+ nvc0_hw_query_update(nvc0->screen->base.client, q);
+
+ if (wait && hq->state != NVC0_HW_QUERY_STATE_READY)
+ nvc0_hw_query_fifo_wait(nvc0, q);
+
+ nouveau_pushbuf_space(push, 32, 2, 0);
+ PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
+ PUSH_REFN (push, buf->bo, buf->domain | NOUVEAU_BO_WR);
+ BEGIN_1IC0(push, NVC0_3D(MACRO_QUERY_BUFFER_WRITE), 9);
+ switch (q->type) {
+ case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: /* XXX what if 64-bit? */
+ case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+ case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
+ PUSH_DATA(push, 0x00000001);
+ break;
+ default:
+ if (result_type == PIPE_QUERY_TYPE_I32)
+ PUSH_DATA(push, 0x7fffffff);
+ else if (result_type == PIPE_QUERY_TYPE_U32)
+ PUSH_DATA(push, 0xffffffff);
+ else
+ PUSH_DATA(push, 0x00000000);
+ break;
+ }
+
+ switch (q->type) {
+ case PIPE_QUERY_SO_STATISTICS:
+ stride = 2;
+ break;
+ case PIPE_QUERY_PIPELINE_STATISTICS:
+ stride = 12;
+ break;
+ case PIPE_QUERY_TIME_ELAPSED:
+ case PIPE_QUERY_TIMESTAMP:
+ qoffset = 8;
+ /* fallthrough */
+ default:
+ assert(index == 0);
+ stride = 1;
+ break;
+ }
+
+ if (hq->is64bit || qoffset) {
+ nouveau_pushbuf_data(push, hq->bo, hq->offset + qoffset + 16 * index,
+ 8 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ if (q->type == PIPE_QUERY_TIMESTAMP) {
+ PUSH_DATA(push, 0);
+ PUSH_DATA(push, 0);
+ } else {
+ nouveau_pushbuf_data(push, hq->bo, hq->offset + qoffset +
+ 16 * (index + stride),
+ 8 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ }
+ } else {
+ nouveau_pushbuf_data(push, hq->bo, hq->offset + 4,
+ 4 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ PUSH_DATA(push, 0);
+ nouveau_pushbuf_data(push, hq->bo, hq->offset + 16 + 4,
+ 4 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ PUSH_DATA(push, 0);
+ }
+
+ if (wait || hq->state == NVC0_HW_QUERY_STATE_READY) {
+ PUSH_DATA(push, 0);
+ PUSH_DATA(push, 0);
+ } else if (hq->is64bit) {
+ PUSH_DATA(push, hq->fence->sequence);
+ nouveau_pushbuf_data(push, nvc0->screen->fence.bo, 0,
+ 4 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ } else {
+ PUSH_DATA(push, hq->sequence);
+ nouveau_pushbuf_data(push, hq->bo, hq->offset,
+ 4 | NVC0_IB_ENTRY_1_NO_PREFETCH);
+ }
+ PUSH_DATAh(push, buf->address + offset);
+ PUSH_DATA (push, buf->address + offset);
+
+ util_range_add(&buf->valid_buffer_range, offset,
+ offset + (result_type >= PIPE_QUERY_TYPE_I64 ? 8 : 4));
+
+ nvc0_resource_validate(buf, NOUVEAU_BO_WR);
+}
+
static const struct nvc0_query_funcs hw_query_funcs = {
.destroy_query = nvc0_hw_destroy_query,
.begin_query = nvc0_hw_begin_query,
.end_query = nvc0_hw_end_query,
.get_query_result = nvc0_hw_get_query_result,
+ .get_query_result_resource = nvc0_hw_get_query_result_resource,
};
struct nvc0_query *
struct nvc0_query *q;
unsigned space = NVC0_HW_QUERY_ALLOC_SPACE;
+ hq = nvc0_hw_sm_create_query(nvc0, type);
+ if (hq) {
+ hq->base.funcs = &hw_query_funcs;
+ return (struct nvc0_query *)hq;
+ }
+
+ hq = nvc0_hw_metric_create_query(nvc0, type);
+ if (hq) {
+ hq->base.funcs = &hw_query_funcs;
+ return (struct nvc0_query *)hq;
+ }
+
hq = CALLOC_STRUCT(nvc0_hw_query);
if (!hq)
return NULL;
q = &hq->base;
q->funcs = &hw_query_funcs;
q->type = type;
+ q->index = index;
switch (q->type) {
case PIPE_QUERY_OCCLUSION_COUNTER:
case PIPE_QUERY_OCCLUSION_PREDICATE:
+ case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
hq->rotate = 32;
space = NVC0_HW_QUERY_ALLOC_SPACE;
break;
space = 512;
break;
case PIPE_QUERY_SO_STATISTICS:
- case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
hq->is64bit = true;
space = 64;
break;
+ case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
+ case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
case PIPE_QUERY_PRIMITIVES_GENERATED:
case PIPE_QUERY_PRIMITIVES_EMITTED:
hq->is64bit = true;
- q->index = index;
space = 32;
break;
case PIPE_QUERY_TIME_ELAPSED:
space = 16;
break;
default:
- if (nvc0->screen->base.device->drm_version >= 0x01000101) {
- if (type >= NVE4_HW_SM_QUERY(0) && type <= NVE4_HW_SM_QUERY_LAST) {
- /* for each MP:
- * [00] = WS0.C0
- * [04] = WS0.C1
- * [08] = WS0.C2
- * [0c] = WS0.C3
- * [10] = WS1.C0
- * [14] = WS1.C1
- * [18] = WS1.C2
- * [1c] = WS1.C3
- * [20] = WS2.C0
- * [24] = WS2.C1
- * [28] = WS2.C2
- * [2c] = WS2.C3
- * [30] = WS3.C0
- * [34] = WS3.C1
- * [38] = WS3.C2
- * [3c] = WS3.C3
- * [40] = MP.C4
- * [44] = MP.C5
- * [48] = MP.C6
- * [4c] = MP.C7
- * [50] = WS0.sequence
- * [54] = WS1.sequence
- * [58] = WS2.sequence
- * [5c] = WS3.sequence
- */
- space = (4 * 4 + 4 + 4) * nvc0->screen->mp_count * sizeof(uint32_t);
- break;
- } else
- if (type >= NVC0_HW_SM_QUERY(0) && type <= NVC0_HW_SM_QUERY_LAST) {
- /* for each MP:
- * [00] = MP.C0
- * [04] = MP.C1
- * [08] = MP.C2
- * [0c] = MP.C3
- * [10] = MP.C4
- * [14] = MP.C5
- * [18] = MP.C6
- * [1c] = MP.C7
- * [20] = MP.sequence
- */
- space = (8 + 1) * nvc0->screen->mp_count * sizeof(uint32_t);
- break;
- }
- }
debug_printf("invalid query type: %u\n", type);
FREE(q);
return NULL;
return q;
}
+int
+nvc0_hw_get_driver_query_info(struct nvc0_screen *screen, unsigned id,
+ struct pipe_driver_query_info *info)
+{
+ int num_hw_sm_queries = 0, num_hw_metric_queries = 0;
+
+ num_hw_sm_queries = nvc0_hw_sm_get_driver_query_info(screen, 0, NULL);
+ num_hw_metric_queries =
+ nvc0_hw_metric_get_driver_query_info(screen, 0, NULL);
+
+ if (!info)
+ return num_hw_sm_queries + num_hw_metric_queries;
+
+ if (id < num_hw_sm_queries)
+ return nvc0_hw_sm_get_driver_query_info(screen, id, info);
+
+ return nvc0_hw_metric_get_driver_query_info(screen,
+ id - num_hw_sm_queries, info);
+}
+
void
nvc0_hw_query_pushbuf_submit(struct nouveau_pushbuf *push,
struct nvc0_query *q, unsigned result_offset)
{
struct nvc0_hw_query *hq = nvc0_hw_query(q);
-#define NVC0_IB_ENTRY_1_NO_PREFETCH (1 << (31 - 8))
-
PUSH_REFN(push, hq->bo, NOUVEAU_BO_RD | NOUVEAU_BO_GART);
- nouveau_pushbuf_space(push, 0, 0, 1);
nouveau_pushbuf_data(push, hq->bo, hq->offset + result_offset, 4 |
NVC0_IB_ENTRY_1_NO_PREFETCH);
}
void
-nvc0_hw_query_fifo_wait(struct nouveau_pushbuf *push, struct nvc0_query *q)
+nvc0_hw_query_fifo_wait(struct nvc0_context *nvc0, struct nvc0_query *q)
{
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_hw_query *hq = nvc0_hw_query(q);
unsigned offset = hq->offset;
- if (q->type == PIPE_QUERY_SO_OVERFLOW_PREDICATE) offset += 0x20;
+ /* ensure the query's fence has been emitted */
+ if (hq->is64bit && hq->fence->state < NOUVEAU_FENCE_STATE_EMITTED)
+ nouveau_fence_emit(hq->fence);
PUSH_SPACE(push, 5);
PUSH_REFN (push, hq->bo, NOUVEAU_BO_GART | NOUVEAU_BO_RD);
BEGIN_NVC0(push, SUBC_3D(NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH), 4);
- PUSH_DATAh(push, hq->bo->offset + offset);
- PUSH_DATA (push, hq->bo->offset + offset);
- PUSH_DATA (push, hq->sequence);
+ if (hq->is64bit) {
+ PUSH_DATAh(push, nvc0->screen->fence.bo->offset);
+ PUSH_DATA (push, nvc0->screen->fence.bo->offset);
+ PUSH_DATA (push, hq->fence->sequence);
+ } else {
+ PUSH_DATAh(push, hq->bo->offset + offset);
+ PUSH_DATA (push, hq->bo->offset + offset);
+ PUSH_DATA (push, hq->sequence);
+ }
PUSH_DATA (push, (1 << 12) |
- NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL);
+ NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL);
}
projects / mesa.git / blobdiff