return 8;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
+ case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
+ case PIPE_CAP_RASTERIZER_SUBPIXEL_BITS:
+ return 8;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return 4;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
return 1024;
case PIPE_CAP_MAX_VERTEX_STREAMS:
return 4;
+ case PIPE_CAP_MAX_GS_INVOCATIONS:
+ return 32;
+ case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
+ return 1 << 27;
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
+ case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
+ return 2047;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return NVC0_MAX_WINDOW_RECTANGLES;
case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
return class_3d >= GM200_3D_CLASS ? 8 : 0;
+ case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+ return 64 * 1024 * 1024;
+ case PIPE_CAP_MAX_VARYINGS:
+ /* NOTE: These only count our slots for GENERIC varyings.
+ * The address space may be larger, but the actual hard limit seems to be
+ * less than what the address space layout permits, so don't add TEXCOORD,
+ * COLOR, etc. here.
+ */
+ return 0x1f0 / 16;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
case PIPE_CAP_QUERY_SO_OVERFLOW:
+ case PIPE_CAP_DEST_SURFACE_SRGB_CONTROL:
return 1;
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
case PIPE_CAP_TGSI_FS_FBFETCH:
return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+ case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+ case PIPE_CAP_TGSI_BALLOT:
+ case PIPE_CAP_BINDLESS_TEXTURE:
+ return class_3d >= NVE4_3D_CLASS;
+ case PIPE_CAP_TGSI_ATOMFADD:
+ return class_3d < GM107_3D_CLASS; /* needs additional lowering */
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
return class_3d >= GM200_3D_CLASS;
- case PIPE_CAP_MAX_GS_INVOCATIONS:
- return 32;
- case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
- return 1 << 27;
case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
return class_3d >= GP100_3D_CLASS;
- case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
- case PIPE_CAP_TGSI_BALLOT:
- case PIPE_CAP_BINDLESS_TEXTURE:
- return class_3d >= NVE4_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
- case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_CONSTBUF0_FLAGS:
case PIPE_CAP_PACKED_UNIFORMS:
case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
- case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET:
+ case PIPE_CAP_MAX_COMBINED_SHADER_BUFFERS:
+ case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTERS:
+ case PIPE_CAP_MAX_COMBINED_HW_ATOMIC_COUNTER_BUFFERS:
+ case PIPE_CAP_SURFACE_SAMPLE_COUNT:
+ case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
+ case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
+ case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
+ case PIPE_CAP_NIR_COMPACT_ARRAYS:
return 0;
case PIPE_CAP_VENDOR_ID:
case PIPE_CAP_UMA:
return 0;
default:
+ debug_printf("%s: unhandled cap %d\n", __func__, param);
return u_pipe_screen_get_param_defaults(pscreen, param);
}
}
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 16;
case PIPE_SHADER_CAP_MAX_INPUTS:
- if (shader == PIPE_SHADER_VERTEX)
- return 32;
- /* NOTE: These only count our slots for GENERIC varyings.
- * The address space may be larger, but the actual hard limit seems to be
- * less than what the address space layout permits, so don't add TEXCOORD,
- * COLOR, etc. here.
- */
- if (shader == PIPE_SHADER_FRAGMENT)
- return 0x1f0 / 16;
- /* Actually this counts CLIPVERTEX, which occupies the last generic slot,
- * and excludes 0x60 per-patch inputs.
- */
return 0x200 / 16;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return 32;
nouveau_heap_destroy(&screen->lib_code);
nouveau_heap_destroy(&screen->text_heap);
- FREE(screen->default_tsc);
FREE(screen->tic.entries);
nouveau_object_del(&screen->eng3d);
push->user_priv = screen;
push->rsvd_kick = 5;
+ /* TODO: could this be higher on Kepler+? how does reclocking vs no
+ * reclocking affect performance?
+ * TODO: could this be higher on Fermi?
+ */
+ if (dev->chipset >= 0xe0)
+ screen->base.transfer_pushbuf_threshold = 1024;
+
screen->base.vidmem_bindings |= PIPE_BIND_CONSTANT_BUFFER |
PIPE_BIND_SHADER_BUFFER |
PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER |
MK_MACRO(NVC0_3D_MACRO_DRAW_ELEMENTS_INDIRECT_COUNT, mme9097_draw_elts_indirect_count);
MK_MACRO(NVC0_3D_MACRO_QUERY_BUFFER_WRITE, mme9097_query_buffer_write);
MK_MACRO(NVC0_3D_MACRO_CONSERVATIVE_RASTER_STATE, mme9097_conservative_raster_state);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER, mme9097_compute_counter);
+ MK_MACRO(NVC0_3D_MACRO_COMPUTE_COUNTER_TO_QUERY, mme9097_compute_counter_to_query);
MK_MACRO(NVC0_CP_MACRO_LAUNCH_GRID_INDIRECT, mme90c0_launch_grid_indirect);
BEGIN_NVC0(push, NVC0_3D(RASTERIZE_ENABLE), 1);
if (!nvc0_blitter_create(screen))
goto fail;
- screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
- screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
-
nouveau_fence_new(&screen->base, &screen->base.fence.current);
return &screen->base;
projects / mesa.git / blobdiff