unsigned sample_count,
unsigned bindings)
{
+ const struct util_format_description *desc = util_format_description(format);
+
if (sample_count > 8)
return false;
if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
return false;
+ /* Short-circuit the rest of the logic -- this is used by the state tracker
+ * to determine valid MS levels in a no-attachments scenario.
+ */
+ if (format == PIPE_FORMAT_NONE && bindings & PIPE_BIND_RENDER_TARGET)
+ return true;
+
if (!util_format_is_supported(format, bindings))
return false;
if (util_format_get_blocksizebits(format) == 3 * 32)
return false;
+ if (bindings & PIPE_BIND_LINEAR)
+ if (util_format_is_depth_or_stencil(format) ||
+ (target != PIPE_TEXTURE_1D &&
+ target != PIPE_TEXTURE_2D &&
+ target != PIPE_TEXTURE_RECT) ||
+ sample_count > 1)
+ return false;
+
+ /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
+ */
+ if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
+ desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
+ /* The claim is that this should work on GM107 but it doesn't. Need to
+ * test further and figure out if it's a nouveau issue or a HW one.
+ nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
+ */
+ nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
+ return false;
+
/* transfers & shared are always supported */
bindings &= ~(PIPE_BIND_TRANSFER_READ |
PIPE_BIND_TRANSFER_WRITE |
+ PIPE_BIND_LINEAR |
PIPE_BIND_SHARED);
+ if (bindings & PIPE_BIND_SHADER_IMAGE && sample_count > 1 &&
+ nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
+ /* MS images are currently unsupported on Maxwell because they have to
+ * be handled explicitly. */
+ return false;
+ }
+
return (( nvc0_format_table[format].usage |
nvc0_vertex_format[format].usage) & bindings) == bindings;
}
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 15;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
+ return 12;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 2048;
case PIPE_CAP_MIN_TEXEL_OFFSET:
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
+ if (class_3d <= NVF0_3D_CLASS)
+ return 430;
return 410;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 8;
return PIPE_ENDIAN_LITTLE;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 30;
+ case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+ return NVC0_MAX_WINDOW_RECTANGLES;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
+ case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_QUERY_BUFFER_OBJECT:
+ case PIPE_CAP_INVALIDATE_BUFFER:
+ case PIPE_CAP_STRING_MARKER:
+ case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+ case PIPE_CAP_CULL_DISTANCE:
+ case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
+ case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_TGSI_VOTE:
+ case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
return 1;
+ case PIPE_CAP_COMPUTE:
+ return (class_3d < GP100_3D_CLASS);
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
- case PIPE_CAP_COMPUTE:
- if (debug_get_bool_option("NVF0_COMPUTE", false))
- return 1;
- return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
- case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_GENERATE_MIPMAP:
- case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
case PIPE_CAP_QUERY_MEMORY_INFO:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
+ case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
return 0;
case PIPE_CAP_VENDOR_ID:
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_FRAGMENT:
- break;
+ case PIPE_SHADER_COMPUTE:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
- if (class_3d >= GM107_3D_CLASS)
- return 0;
- break;
- case PIPE_SHADER_COMPUTE:
- if (!debug_get_bool_option("NVF0_COMPUTE", false))
- if (class_3d > NVE4_3D_CLASS)
- return 0;
break;
default:
return 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- if (class_3d >= NVE4_3D_CLASS)
- return 0;
return 1 << PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
return 65536;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- if (shader == PIPE_SHADER_COMPUTE && class_3d >= NVE4_3D_CLASS)
- return NVE4_MAX_PIPE_CONSTBUFS_COMPUTE;
return NVC0_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
- return 0;
+ return 1;
case PIPE_SHADER_CAP_SUBROUTINES:
return 1;
case PIPE_SHADER_CAP_INTEGERS:
return 1;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
return 1;
- case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
+ return 1;
+ case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return NVC0_MAX_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
- return 16; /* would be 32 in linked (OpenGL-style) mode */
+ return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
- return 16; /* XXX not sure if more are really safe */
+ return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ if (class_3d == NVE4_3D_CLASS || class_3d == NVF0_3D_CLASS)
+ return NVC0_MAX_IMAGES;
+ if (class_3d < NVE4_3D_CLASS)
+ if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
+ return NVC0_MAX_IMAGES;
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
static int
nvc0_screen_get_compute_param(struct pipe_screen *pscreen,
+ enum pipe_shader_ir ir_type,
enum pipe_compute_cap param, void *data)
{
struct nvc0_screen *screen = nvc0_screen(pscreen);
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
RET((uint64_t []) { 1ULL << 40 });
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
- RET((uint64_t []) { 48 << 10 });
+ switch (obj_class) {
+ case GM200_COMPUTE_CLASS:
+ RET((uint64_t []) { 96 << 10 });
+ break;
+ case GM107_COMPUTE_CLASS:
+ RET((uint64_t []) { 64 << 10 });
+ break;
+ default:
+ RET((uint64_t []) { 48 << 10 });
+ break;
+ }
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
RET((uint64_t []) { 512 << 10 });
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
RET((uint32_t []) { screen->mp_count_compute });
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ RET((uint32_t []) { 64 });
default:
return 0;
}
nouveau_bo_ref(NULL, &screen->txc);
nouveau_bo_ref(NULL, &screen->fence.bo);
nouveau_bo_ref(NULL, &screen->poly_cache);
- nouveau_bo_ref(NULL, &screen->parm);
nouveau_heap_destroy(&screen->lib_code);
nouveau_heap_destroy(&screen->text_heap);
case 0xd0:
return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
case 0xe0:
- return nve4_screen_compute_setup(screen, screen->base.pushbuf);
case 0xf0:
case 0x100:
case 0x110:
- if (debug_get_bool_option("NVF0_COMPUTE", false))
- return nve4_screen_compute_setup(screen, screen->base.pushbuf);
case 0x120:
+ return nve4_screen_compute_setup(screen, screen->base.pushbuf);
+ case 0x130:
return 0;
default:
return -1;
case 0x100:
case 0x110:
case 0x120:
+ case 0x130:
break;
default:
return NULL;
pscreen->destroy = nvc0_screen_destroy;
ret = nouveau_screen_init(&screen->base, dev);
- if (ret) {
- nvc0_screen_destroy(pscreen);
- return NULL;
- }
+ if (ret)
+ FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
chan = screen->base.channel;
push = screen->base.pushbuf;
push->user_priv = screen;
ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
nouveau_bo_map(screen->fence.bo, 0, NULL);
screen->fence.map = screen->fence.bo->map;
screen->base.fence.emit = nvc0_screen_fence_emit;
PUSH_DATA (push, screen->nvsw->handle);
switch (dev->chipset & ~0xf) {
+ case 0x130:
case 0x120:
case 0x110:
case 0x100:
PUSH_DATA (push, screen->fence.bo->offset + 16);
switch (dev->chipset & ~0xf) {
+ case 0x130:
+ obj_class = GP100_3D_CLASS;
+ break;
case 0x120:
obj_class = GM200_3D_CLASS;
break;
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
&screen->text);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
/* XXX: getting a page fault at the end of the code buffer every few
* launches, don't use the last 256 bytes to work around them - prefetch ?
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
&screen->uniform_bo);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
/* TIC and TSC entries for each unit (nve4+ only) */
/* auxiliary constants (6 user clip planes, base instance id) */
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, 1024);
- PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
- PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (i << 10));
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
PUSH_DATA (push, (15 << 4) | 1);
if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
unsigned j;
BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
- PUSH_DATA (push, 0);
+ PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
for (j = 0; j < 8; ++j)
PUSH_DATA(push, j);
} else {
BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
PUSH_DATA (push, 0x54);
}
+
+ /* MS sample coordinate offsets: these do not work with _ALT modes ! */
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
+ PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
+ PUSH_DATA (push, 0); /* 0 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 1); /* 1 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 0); /* 2 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 1); /* 3 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 2); /* 4 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 3); /* 5 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 2); /* 6 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 3); /* 7 */
+ PUSH_DATA (push, 1);
}
BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
PUSH_DATA (push, 0);
/* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
PUSH_DATA (push, 256);
- PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
- PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
BEGIN_1IC0(push, NVC0_3D(CB_POS), 5);
PUSH_DATA (push, 0);
PUSH_DATAf(push, 0.0f);
PUSH_DATAf(push, 0.0f);
PUSH_DATAf(push, 0.0f);
BEGIN_NVC0(push, NVC0_3D(VERTEX_RUNOUT_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
- PUSH_DATA (push, screen->uniform_bo->offset + (6 << 16) + (6 << 10));
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_RUNOUT_INFO);
if (screen->base.drm->version >= 0x01000101) {
ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
- if (ret) {
- NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
- goto fail;
- }
+ if (ret)
+ FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
} else {
if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
value = (8 << 8) | 4;
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
&screen->poly_cache);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->poly_cache->offset);
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
&screen->txc);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset);
projects / mesa.git / blobdiff