#include "util/u_format_s3tc.h"
#include "pipe/p_screen.h"
-#include "vl/vl_decoder.h"
-#include "vl/vl_video_buffer.h"
-
#include "nouveau_vp3_video.h"
#include "nvc0/nvc0_context.h"
#include "nvc0/mme/com9097.mme.h"
#include "nvc0/mme/com90c0.mme.h"
+#include "nv50/g80_texture.xml.h"
+
static boolean
nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
enum pipe_format format,
nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
return false;
- /* transfers & shared are always supported */
- bindings &= ~(PIPE_BIND_TRANSFER_READ |
- PIPE_BIND_TRANSFER_WRITE |
- PIPE_BIND_LINEAR |
+ /* shared is always supported */
+ bindings &= ~(PIPE_BIND_LINEAR |
PIPE_BIND_SHARED);
+ if (bindings & PIPE_BIND_SHADER_IMAGE) {
+ if (sample_count > 1 &&
+ nouveau_screen(pscreen)->class_3d >= GM107_3D_CLASS) {
+ /* MS images are currently unsupported on Maxwell because they have to
+ * be handled explicitly. */
+ return false;
+ }
+
+ if (format == PIPE_FORMAT_B8G8R8A8_UNORM &&
+ nouveau_screen(pscreen)->class_3d < NVE4_3D_CLASS) {
+ /* This should work on Fermi, but for currently unknown reasons it
+ * does not and results in breaking reads from pbos. */
+ return false;
+ }
+ }
+
return (( nvc0_format_table[format].usage |
nvc0_vertex_format[format].usage) & bindings) == bindings;
}
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return 15;
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
- return (class_3d >= NVE4_3D_CLASS) ? 13 : 12;
+ return 12;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 2048;
case PIPE_CAP_MIN_TEXEL_OFFSET:
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
return 128 * 1024 * 1024;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
- return 410;
+ return 430;
case PIPE_CAP_MAX_RENDER_TARGETS:
return 8;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
- return 16; /* 256 for binding as RT, but that's not possible in GL */
+ if (class_3d < GM107_3D_CLASS)
+ return 256; /* IMAGE bindings require alignment to 256 */
+ return 16;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 16;
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
return PIPE_ENDIAN_LITTLE;
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
return 30;
+ case PIPE_CAP_MAX_WINDOW_RECTANGLES:
+ return NVC0_MAX_WINDOW_RECTANGLES;
/* supported caps */
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
+ case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_QUERY_TIME_ELAPSED:
case PIPE_CAP_OCCLUSION_QUERY:
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+ case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
case PIPE_CAP_DRAW_INDIRECT:
case PIPE_CAP_USER_CONSTANT_BUFFERS:
- case PIPE_CAP_USER_INDEX_BUFFERS:
case PIPE_CAP_USER_VERTEX_BUFFERS:
case PIPE_CAP_TEXTURE_QUERY_LOD:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_INVALIDATE_BUFFER:
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
+ case PIPE_CAP_CULL_DISTANCE:
+ case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
+ case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_TGSI_VOTE:
+ case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
+ case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+ case PIPE_CAP_TGSI_MUL_ZERO_WINS:
+ case PIPE_CAP_DOUBLES:
+ case PIPE_CAP_INT64:
+ case PIPE_CAP_TGSI_TEX_TXF_LZ:
+ case PIPE_CAP_TGSI_CLOCK:
+ case PIPE_CAP_COMPUTE:
+ case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
+ case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return (class_3d >= NVE4_3D_CLASS) ? 1 : 0;
- case PIPE_CAP_COMPUTE:
- if (debug_get_bool_option("NVF0_COMPUTE", false))
- return 1;
- return (class_3d <= NVE4_3D_CLASS) ? 1 : 0;
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return nouveau_screen(pscreen)->vram_domain & NOUVEAU_BO_VRAM ? 1 : 0;
+ case PIPE_CAP_TGSI_FS_FBFETCH:
+ return class_3d >= NVE4_3D_CLASS; /* needs testing on fermi */
+ case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
+ case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
+ case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
+ return class_3d >= GM200_3D_CLASS;
+ case PIPE_CAP_TGSI_BALLOT:
+ return class_3d >= NVE4_3D_CLASS;
/* unsupported caps */
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
- case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
case PIPE_CAP_FAKE_SW_MSAA:
case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
case PIPE_CAP_VERTEXID_NOBASE:
case PIPE_CAP_PCI_BUS:
case PIPE_CAP_PCI_DEVICE:
case PIPE_CAP_PCI_FUNCTION:
- case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
+ case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
+ case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
+ case PIPE_CAP_NATIVE_FENCE_FD:
+ case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
+ case PIPE_CAP_INT64_DIVMOD:
+ case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
return 0;
case PIPE_CAP_VENDOR_ID:
}
static int
-nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
+nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
+ enum pipe_shader_type shader,
enum pipe_shader_cap param)
{
const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
case PIPE_SHADER_FRAGMENT:
- break;
+ case PIPE_SHADER_COMPUTE:
case PIPE_SHADER_TESS_CTRL:
case PIPE_SHADER_TESS_EVAL:
- if (class_3d >= GM107_3D_CLASS)
- return 0;
- break;
- case PIPE_SHADER_COMPUTE:
- if (!debug_get_bool_option("NVF0_COMPUTE", false))
- if (class_3d > NVE4_3D_CLASS)
- return 0;
break;
default:
return 0;
case PIPE_SHADER_CAP_PREFERRED_IR:
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- if (class_3d == NVF0_3D_CLASS &&
- !debug_get_bool_option("NVF0_COMPUTE", false))
- return 0;
return 1 << PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
return shader != PIPE_SHADER_FRAGMENT;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
- return shader != PIPE_SHADER_FRAGMENT || class_3d < GM107_3D_CLASS;
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
return 1;
- case PIPE_SHADER_CAP_MAX_PREDS:
- return 0;
case PIPE_SHADER_CAP_MAX_TEMPS:
return NVC0_CAP_MAX_PROGRAM_TEMPS;
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INTEGERS:
return 1;
- case PIPE_SHADER_CAP_DOUBLES:
- return 1;
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
return 1;
+ case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
+ return 1;
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
+ case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
return 0;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return NVC0_MAX_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
- return 16; /* would be 32 in linked (OpenGL-style) mode */
+ return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
- return 16; /* XXX not sure if more are really safe */
+ return (class_3d >= NVE4_3D_CLASS) ? 32 : 16;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
+ if (class_3d >= NVE4_3D_CLASS)
+ return NVC0_MAX_IMAGES;
+ if (shader == PIPE_SHADER_FRAGMENT || shader == PIPE_SHADER_COMPUTE)
+ return NVC0_MAX_IMAGES;
return 0;
default:
NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
RET(((uint64_t []) { 1024, 1024, 64 }));
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
RET((uint64_t []) { 1024 });
+ case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
+ if (obj_class >= NVE4_COMPUTE_CLASS) {
+ RET((uint64_t []) { 1024 });
+ } else {
+ RET((uint64_t []) { 512 });
+ }
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE: /* g[] */
RET((uint64_t []) { 1ULL << 40 });
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE: /* s[] */
- RET((uint64_t []) { 48 << 10 });
+ switch (obj_class) {
+ case GM200_COMPUTE_CLASS:
+ RET((uint64_t []) { 96 << 10 });
+ break;
+ case GM107_COMPUTE_CLASS:
+ RET((uint64_t []) { 64 << 10 });
+ break;
+ default:
+ RET((uint64_t []) { 48 << 10 });
+ break;
+ }
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE: /* l[] */
RET((uint64_t []) { 512 << 10 });
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE: /* c[], arbitrary limit */
RET((uint32_t []) { screen->mp_count_compute });
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
RET((uint32_t []) { 512 }); /* FIXME: arbitrary limit */
+ case PIPE_COMPUTE_CAP_ADDRESS_BITS:
+ RET((uint32_t []) { 64 });
default:
return 0;
}
nouveau_bo_ref(NULL, &screen->txc);
nouveau_bo_ref(NULL, &screen->fence.bo);
nouveau_bo_ref(NULL, &screen->poly_cache);
- nouveau_bo_ref(NULL, &screen->parm);
nouveau_heap_destroy(&screen->lib_code);
nouveau_heap_destroy(&screen->text_heap);
+ FREE(screen->default_tsc);
FREE(screen->tic.entries);
nouveau_object_del(&screen->eng3d);
case 0xd0:
return nvc0_screen_compute_setup(screen, screen->base.pushbuf);
case 0xe0:
- return nve4_screen_compute_setup(screen, screen->base.pushbuf);
case 0xf0:
case 0x100:
case 0x110:
case 0x120:
- if (debug_get_bool_option("NVF0_COMPUTE", false))
- return nve4_screen_compute_setup(screen, screen->base.pushbuf);
+ case 0x130:
+ return nve4_screen_compute_setup(screen, screen->base.pushbuf);
default:
return -1;
}
}
-bool
+static int
nvc0_screen_resize_tls_area(struct nvc0_screen *screen,
uint32_t lpos, uint32_t lneg, uint32_t cstack)
{
if (size >= (1 << 20)) {
NOUVEAU_ERR("requested TLS size too large: 0x%"PRIx64"\n", size);
- return false;
+ return -1;
}
size *= (screen->base.device->chipset >= 0xe0) ? 64 : 48; /* max warps */
ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base), 1 << 17, size,
NULL, &bo);
- if (ret) {
- NOUVEAU_ERR("failed to allocate TLS area, size: 0x%"PRIx64"\n", size);
- return false;
- }
+ if (ret)
+ return ret;
nouveau_bo_ref(NULL, &screen->tls);
screen->tls = bo;
- return true;
+ return 0;
+}
+
+int
+nvc0_screen_resize_text_area(struct nvc0_screen *screen, uint64_t size)
+{
+ struct nouveau_pushbuf *push = screen->base.pushbuf;
+ struct nouveau_bo *bo;
+ int ret;
+
+ ret = nouveau_bo_new(screen->base.device, NV_VRAM_DOMAIN(&screen->base),
+ 1 << 17, size, NULL, &bo);
+ if (ret)
+ return ret;
+
+ nouveau_bo_ref(NULL, &screen->text);
+ screen->text = bo;
+
+ nouveau_heap_destroy(&screen->lib_code);
+ nouveau_heap_destroy(&screen->text_heap);
+
+ /* XXX: getting a page fault at the end of the code buffer every few
+ * launches, don't use the last 256 bytes to work around them - prefetch ?
+ */
+ nouveau_heap_init(&screen->text_heap, 0, size - 0x100);
+
+ /* update the code segment setup */
+ BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, screen->text->offset);
+ PUSH_DATA (push, screen->text->offset);
+ if (screen->compute) {
+ BEGIN_NVC0(push, NVC0_CP(CODE_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, screen->text->offset);
+ PUSH_DATA (push, screen->text->offset);
+ }
+
+ return 0;
}
#define FAIL_SCREEN_INIT(str, err) \
case 0x100:
case 0x110:
case 0x120:
+ case 0x130:
break;
default:
return NULL;
pscreen->destroy = nvc0_screen_destroy;
ret = nouveau_screen_init(&screen->base, dev);
- if (ret) {
- nvc0_screen_destroy(pscreen);
- return NULL;
- }
+ if (ret)
+ FAIL_SCREEN_INIT("Base screen init failed: %d\n", ret);
chan = screen->base.channel;
push = screen->base.pushbuf;
push->user_priv = screen;
ret = nouveau_bo_new(dev, flags, 0, 4096, NULL, &screen->fence.bo);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating fence BO: %d\n", ret);
nouveau_bo_map(screen->fence.bo, 0, NULL);
screen->fence.map = screen->fence.bo->map;
screen->base.fence.emit = nvc0_screen_fence_emit;
PUSH_DATA (push, screen->nvsw->handle);
switch (dev->chipset & ~0xf) {
+ case 0x130:
case 0x120:
case 0x110:
case 0x100:
PUSH_DATA (push, screen->fence.bo->offset + 16);
switch (dev->chipset & ~0xf) {
+ case 0x130:
+ switch (dev->chipset) {
+ case 0x130:
+ case 0x13b:
+ obj_class = GP100_3D_CLASS;
+ break;
+ default:
+ obj_class = GP102_3D_CLASS;
+ break;
+ }
+ break;
case 0x120:
obj_class = GM200_3D_CLASS;
break;
screen->base.drm->version >= 0x01000101);
BEGIN_NVC0(push, NVC0_3D(RT_COMP_ENABLE(0)), 8);
for (i = 0; i < 8; ++i)
- PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
+ PUSH_DATA(push, screen->base.drm->version >= 0x01000101);
BEGIN_NVC0(push, NVC0_3D(RT_CONTROL), 1);
PUSH_DATA (push, 1);
nvc0_magic_3d_init(push, screen->eng3d->oclass);
- ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
- &screen->text);
+ ret = nvc0_screen_resize_text_area(screen, 1 << 19);
if (ret)
- goto fail;
-
- /* XXX: getting a page fault at the end of the code buffer every few
- * launches, don't use the last 256 bytes to work around them - prefetch ?
- */
- nouveau_heap_init(&screen->text_heap, 0, (1 << 20) - 0x100);
+ FAIL_SCREEN_INIT("Error allocating TEXT area: %d\n", ret);
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 12, 7 << 16, NULL,
&screen->uniform_bo);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating uniform BO: %d\n", ret);
PUSH_REFN (push, screen->uniform_bo, NV_VRAM_DOMAIN(&screen->base) | NOUVEAU_BO_WR);
- for (i = 0; i < 5; ++i) {
- /* TIC and TSC entries for each unit (nve4+ only) */
- /* auxiliary constants (6 user clip planes, base instance id) */
- BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, 1024);
- PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
- PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
- BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
- PUSH_DATA (push, (15 << 4) | 1);
- if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
- unsigned j;
- BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
- PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
- for (j = 0; j < 8; ++j)
- PUSH_DATA(push, j);
- } else {
- BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
- PUSH_DATA (push, 0x54);
- }
- }
- BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
- PUSH_DATA (push, 0);
-
/* return { 0.0, 0.0, 0.0, 0.0 } for out-of-bounds vtxbuf access */
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
PUSH_DATA (push, 256);
if (screen->base.drm->version >= 0x01000101) {
ret = nouveau_getparam(dev, NOUVEAU_GETPARAM_GRAPH_UNITS, &value);
- if (ret) {
- NOUVEAU_ERR("NOUVEAU_GETPARAM_GRAPH_UNITS failed.\n");
- goto fail;
- }
+ if (ret)
+ FAIL_SCREEN_INIT("NOUVEAU_GETPARAM_GRAPH_UNITS failed: %d\n", ret);
} else {
if (dev->chipset >= 0xe0 && dev->chipset < 0xf0)
value = (8 << 8) | 4;
screen->mp_count = value >> 8;
screen->mp_count_compute = screen->mp_count;
- nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
+ ret = nvc0_screen_resize_tls_area(screen, 128 * 16, 0, 0x200);
+ if (ret)
+ FAIL_SCREEN_INIT("Error allocating TLS area: %d\n", ret);
- BEGIN_NVC0(push, NVC0_3D(CODE_ADDRESS_HIGH), 2);
- PUSH_DATAh(push, screen->text->offset);
- PUSH_DATA (push, screen->text->offset);
BEGIN_NVC0(push, NVC0_3D(TEMP_ADDRESS_HIGH), 4);
PUSH_DATAh(push, screen->tls->offset);
PUSH_DATA (push, screen->tls->offset);
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 20, NULL,
&screen->poly_cache);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating poly cache BO: %d\n", ret);
BEGIN_NVC0(push, NVC0_3D(VERTEX_QUARANTINE_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->poly_cache->offset);
ret = nouveau_bo_new(dev, NV_VRAM_DOMAIN(&screen->base), 1 << 17, 1 << 17, NULL,
&screen->txc);
if (ret)
- goto fail;
+ FAIL_SCREEN_INIT("Error allocating txc BO: %d\n", ret);
BEGIN_NVC0(push, NVC0_3D(TIC_ADDRESS_HIGH), 3);
PUSH_DATAh(push, screen->txc->offset);
if (nvc0_screen_init_compute(screen))
goto fail;
+ /* XXX: Compute and 3D are somehow aliased on Fermi. */
+ for (i = 0; i < 5; ++i) {
+ /* TIC and TSC entries for each unit (nve4+ only) */
+ /* auxiliary constants (6 user clip planes, base instance id) */
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(i));
+ BEGIN_NVC0(push, NVC0_3D(CB_BIND(i)), 1);
+ PUSH_DATA (push, (15 << 4) | 1);
+ if (screen->eng3d->oclass >= NVE4_3D_CLASS) {
+ unsigned j;
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 9);
+ PUSH_DATA (push, NVC0_CB_AUX_UNK_INFO);
+ for (j = 0; j < 8; ++j)
+ PUSH_DATA(push, j);
+ } else {
+ BEGIN_NVC0(push, NVC0_3D(TEX_LIMITS(i)), 1);
+ PUSH_DATA (push, 0x54);
+ }
+
+ /* MS sample coordinate offsets: these do not work with _ALT modes ! */
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 2 * 8);
+ PUSH_DATA (push, NVC0_CB_AUX_MS_INFO);
+ PUSH_DATA (push, 0); /* 0 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 1); /* 1 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 0); /* 2 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 1); /* 3 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 2); /* 4 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 3); /* 5 */
+ PUSH_DATA (push, 0);
+ PUSH_DATA (push, 2); /* 6 */
+ PUSH_DATA (push, 1);
+ PUSH_DATA (push, 3); /* 7 */
+ PUSH_DATA (push, 1);
+ }
+ BEGIN_NVC0(push, NVC0_3D(LINKED_TSC), 1);
+ PUSH_DATA (push, 0);
+
PUSH_KICK (push);
screen->tic.entries = CALLOC(4096, sizeof(void *));
if (!nvc0_blitter_create(screen))
goto fail;
- nouveau_fence_new(&screen->base, &screen->base.fence.current, false);
+ screen->default_tsc = CALLOC_STRUCT(nv50_tsc_entry);
+ screen->default_tsc->tsc[0] = G80_TSC_0_SRGB_CONVERSION;
+
+ nouveau_fence_new(&screen->base, &screen->base.fence.current);
return &screen->base;
projects / mesa.git / blobdiff