nvc0: enable texture query lod

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.c

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index ff7890bbac46bee6214e9841ea7d2b0b6a2b2b3a..fa3145eacde63e09ca684a181536e5415e5d5d8a 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -71,8 +71,6 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    const uint16_t class_3d = nouveau_screen(pscreen)->class_3d;
 
    switch (param) {
-   case PIPE_CAP_MAX_COMBINED_SAMPLERS:
-      return 16 * 5;
    case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
    case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
       return 15;
@@ -88,6 +86,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_TEXTURE_SWIZZLE:
    case PIPE_CAP_TEXTURE_SHADOW_MAP:
    case PIPE_CAP_NPOT_TEXTURES:
+   case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
    case PIPE_CAP_ANISOTROPIC_FILTER:
    case PIPE_CAP_SEAMLESS_CUBE_MAP:
    case PIPE_CAP_CUBE_MAP_ARRAY:
@@ -106,7 +105,7 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_SM3:
       return 1;
    case PIPE_CAP_GLSL_FEATURE_LEVEL:
-      return 150;
+      return 330;
    case PIPE_CAP_MAX_RENDER_TARGETS:
       return 8;
    case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
@@ -126,6 +125,9 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
    case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
    case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
       return 128;
+   case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
+   case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
+      return 1024;
    case PIPE_CAP_BLEND_EQUATION_SEPARATE:
    case PIPE_CAP_INDEP_BLEND_ENABLE:
    case PIPE_CAP_INDEP_BLEND_FUNC:
@@ -171,6 +173,16 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
       return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
    case PIPE_CAP_ENDIANNESS:
       return PIPE_ENDIAN_LITTLE;
+   case PIPE_CAP_TGSI_VS_LAYER:
+   case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
+   case PIPE_CAP_TEXTURE_GATHER_SM5:
+   case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
+   case PIPE_CAP_FAKE_SW_MSAA:
+      return 0;
+   case PIPE_CAP_MAX_VIEWPORTS:
+      return 1;
+   case PIPE_CAP_TEXTURE_QUERY_LOD:
+      return 1;
    default:
       NOUVEAU_ERR("unknown PIPE_CAP %d\n", param);
       return 0;
@@ -252,10 +264,8 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader,
       return 1;
    case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
       return 16; /* would be 32 in linked (OpenGL-style) mode */
-      /*
-   case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLER_VIEWS:
-      return 32;
-      */
+   case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
+      return 16; /* XXX not sure if more are really safe */
    default:
       NOUVEAU_ERR("unknown PIPE_SHADER_CAP %d\n", param);
       return 0;
@@ -329,8 +339,18 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
 {
    struct nvc0_screen *screen = nvc0_screen(pscreen);
 
+   if (!nouveau_drm_screen_unref(&screen->base))
+      return;
+
    if (screen->base.fence.current) {
-      nouveau_fence_wait(screen->base.fence.current);
+      struct nouveau_fence *current = NULL;
+
+      /* nouveau_fence_wait will create a new current fence, so wait on the
+       * _current_ one, and remove both.
+       */
+      nouveau_fence_ref(screen->base.fence.current, &current);
+      nouveau_fence_wait(current);
+      nouveau_fence_ref(NULL, &current);
       nouveau_fence_ref(NULL, &screen->base.fence.current);
    }
    if (screen->base.pushbuf)
@@ -362,6 +382,7 @@ nvc0_screen_destroy(struct pipe_screen *pscreen)
    nouveau_object_del(&screen->eng2d);
    nouveau_object_del(&screen->m2mf);
    nouveau_object_del(&screen->compute);
+   nouveau_object_del(&screen->nvsw);
 
    nouveau_screen_fini(&screen->base);
 
@@ -477,7 +498,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
 {
    screen->base.base.get_compute_param = nvc0_screen_get_compute_param;
 
-   switch (screen->base.device->chipset & 0xf0) {
+   switch (screen->base.device->chipset & ~0xf) {
    case 0xc0:
    case 0xd0:
       /* Using COMPUTE has weird effects on 3D state, we need to
@@ -488,6 +509,7 @@ nvc0_screen_init_compute(struct nvc0_screen *screen)
       return 0;
    case 0xe0:
    case 0xf0:
+   case 0x100:
       return nve4_screen_compute_setup(screen, screen->base.pushbuf);
    default:
       return -1;
@@ -549,6 +571,7 @@ nvc0_screen_create(struct nouveau_device *dev)
    case 0xd0:
    case 0xe0:
    case 0xf0:
+   case 0x100:
       break;
    default:
       return NULL;
@@ -596,7 +619,16 @@ nvc0_screen_create(struct nouveau_device *dev)
    screen->base.fence.emit = nvc0_screen_fence_emit;
    screen->base.fence.update = nvc0_screen_fence_update;
 
-   switch (dev->chipset & 0xf0) {
+
+   ret = nouveau_object_new(chan,
+                            (dev->chipset < 0xe0) ? 0x1f906e : 0x906e, 0x906e,
+                            NULL, 0, &screen->nvsw);
+   if (ret)
+      FAIL_SCREEN_INIT("Error creating SW object: %d\n", ret);
+
+
+   switch (dev->chipset & ~0xf) {
+   case 0x100:
    case 0xf0:
       obj_class = NVF0_P2MF_CLASS;
       break;
@@ -643,7 +675,8 @@ nvc0_screen_create(struct nouveau_device *dev)
    PUSH_DATAh(push, screen->fence.bo->offset + 16);
    PUSH_DATA (push, screen->fence.bo->offset + 16);
 
-   switch (dev->chipset & 0xf0) {
+   switch (dev->chipset & ~0xf) {
+   case 0x100:
    case 0xf0:
       obj_class = NVF0_3D_CLASS;
       break;
@@ -651,10 +684,11 @@ nvc0_screen_create(struct nouveau_device *dev)
       obj_class = NVE4_3D_CLASS;
       break;
    case 0xd0:
+      obj_class = NVC8_3D_CLASS;
+      break;
    case 0xc0:
    default:
       switch (dev->chipset) {
-      case 0xd9:
       case 0xc8:
          obj_class = NVC8_3D_CLASS;
          break;
@@ -742,6 +776,8 @@ nvc0_screen_create(struct nouveau_device *dev)
    if (ret)
       goto fail;
 
+   PUSH_REFN (push, screen->uniform_bo, NOUVEAU_BO_VRAM | NOUVEAU_BO_WR);
+
    for (i = 0; i < 5; ++i) {
       /* TIC and TSC entries for each unit (nve4+ only) */
       /* auxiliary constants (6 user clip planes, base instance id) */