Added few more stubs so that control reaches to DestroyDevice().

[mesa.git] / src / gallium / drivers / nouveau / nvc0 / nvc0_screen.h

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
index 1a56177815c261bb9c7e1b7ebb90d9d42a042a6e..392980562bd3b4d0f49485a5f3bcab15ed15a4a5 100644 (file)
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.h
@@ -13,10 +13,12 @@
 
 #define NVC0_TIC_MAX_ENTRIES 2048
 #define NVC0_TSC_MAX_ENTRIES 2048
+#define NVE4_IMG_MAX_HANDLES 512
 
-/* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
-#define NVC0_MAX_PIPE_CONSTBUFS         14
-#define NVE4_MAX_PIPE_CONSTBUFS_COMPUTE  7
+/* doesn't count driver-reserved slot */
+#define NVC0_MAX_PIPE_CONSTBUFS 15
+#define NVC0_MAX_CONST_BUFFERS  16
+#define NVC0_MAX_CONSTBUF_SIZE  65536
 
 #define NVC0_MAX_SURFACE_SLOTS 16
 
@@ -24,6 +26,9 @@
 
 #define NVC0_MAX_BUFFERS 32
 
+#define NVC0_MAX_IMAGES 8
+
+#define NVC0_MAX_WINDOW_RECTANGLES 8
 
 struct nvc0_context;
 
@@ -48,11 +53,17 @@ struct nvc0_graph_state {
    uint8_t num_textures[6];
    uint8_t num_samplers[6];
    uint8_t tls_required; /* bitmask of shader types using l[] */
-   uint8_t c14_bound; /* whether immediate array constbuf is bound */
    uint8_t clip_enable;
    uint32_t clip_mode;
-   uint32_t uniform_buffer_bound[5];
+   bool uniform_buffer_bound[6];
    struct nvc0_transform_feedback_state *tfb;
+   bool seamless_cube_map;
+   bool post_depth_coverage;
+};
+
+struct nvc0_cb_binding {
+   uint64_t addr;
+   int size;
 };
 
 struct nvc0_screen {
@@ -64,8 +75,7 @@ struct nvc0_screen {
    int num_occlusion_queries_active;
 
    struct nouveau_bo *text;
-   struct nouveau_bo *parm;       /* for COMPUTE */
-   struct nouveau_bo *uniform_bo; /* for 3D */
+   struct nouveau_bo *uniform_bo;
    struct nouveau_bo *tls;
    struct nouveau_bo *txc; /* TIC (offset 0) and TSC (65536) */
    struct nouveau_bo *poly_cache;
@@ -83,6 +93,7 @@ struct nvc0_screen {
       void **entries;
       int next;
       uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
+      bool maxwell;
    } tic;
 
    struct {
@@ -91,6 +102,11 @@ struct nvc0_screen {
       uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
    } tsc;
 
+   struct {
+      struct pipe_image_view **entries;
+      int next;
+   } img;
+
    struct {
       struct nouveau_bo *bo;
       uint32_t *map;
@@ -103,6 +119,9 @@ struct nvc0_screen {
       bool mp_counters_enabled;
    } pm;
 
+   /* only maintained on Maxwell+ */
+   struct nvc0_cb_binding cb_bindings[5][NVC0_MAX_CONST_BUFFERS];
+
    struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
    struct nouveau_object *eng2d;
    struct nouveau_object *m2mf;
@@ -133,8 +152,10 @@ int nvc0_screen_tsc_alloc(struct nvc0_screen *, void *);
 int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
 
-bool nvc0_screen_resize_tls_area(struct nvc0_screen *, uint32_t lpos,
-                                 uint32_t lneg, uint32_t cstack);
+int nvc0_screen_resize_text_area(struct nvc0_screen *, uint64_t);
+
+// 3D Only
+void nvc0_screen_bind_cb_3d(struct nvc0_screen *, bool *, int, int, int, uint64_t);
 
 static inline void
 nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
@@ -164,16 +185,33 @@ nvc0_resource_validate(struct nv04_resource *res, uint32_t flags)
 
 struct nvc0_format {
    uint32_t rt;
-   uint32_t tic;
+   struct {
+      unsigned format:7;
+      unsigned type_r:3;
+      unsigned type_g:3;
+      unsigned type_b:3;
+      unsigned type_a:3;
+      unsigned src_x:3;
+      unsigned src_y:3;
+      unsigned src_z:3;
+      unsigned src_w:3;
+   } tic;
+   uint32_t usage;
+};
+
+struct nvc0_vertex_format {
    uint32_t vtx;
    uint32_t usage;
 };
 
 extern const struct nvc0_format nvc0_format_table[];
+extern const struct nvc0_vertex_format nvc0_vertex_format[];
 
 static inline void
 nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
 {
+   if (tic->bindless)
+      return;
    if (tic->id >= 0)
       screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
 }