#define NVC0_TIC_MAX_ENTRIES 2048
#define NVC0_TSC_MAX_ENTRIES 2048
+#define NVE4_IMG_MAX_HANDLES 512
-/* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
-#define NVC0_MAX_PIPE_CONSTBUFS 14
+/* doesn't count driver-reserved slot */
+#define NVC0_MAX_PIPE_CONSTBUFS 15
+#define NVC0_MAX_CONST_BUFFERS 16
+#define NVC0_MAX_CONSTBUF_SIZE 65536
#define NVC0_MAX_SURFACE_SLOTS 16
uint8_t num_textures[6];
uint8_t num_samplers[6];
uint8_t tls_required; /* bitmask of shader types using l[] */
- uint8_t c14_bound; /* whether immediate array constbuf is bound */
uint8_t clip_enable;
uint32_t clip_mode;
- uint32_t uniform_buffer_bound[6];
+ bool uniform_buffer_bound[6];
struct nvc0_transform_feedback_state *tfb;
bool seamless_cube_map;
+ bool post_depth_coverage;
+};
+
+struct nvc0_cb_binding {
+ uint64_t addr;
+ int size;
};
struct nvc0_screen {
uint32_t lock[NVC0_TSC_MAX_ENTRIES / 32];
} tsc;
+ struct {
+ struct pipe_image_view **entries;
+ int next;
+ } img;
+
struct {
struct nouveau_bo *bo;
uint32_t *map;
bool mp_counters_enabled;
} pm;
+ /* only maintained on Maxwell+ */
+ struct nvc0_cb_binding cb_bindings[5][NVC0_MAX_CONST_BUFFERS];
+
struct nouveau_object *eng3d; /* sqrt(1/2)|kepler> + sqrt(1/2)|fermi> */
struct nouveau_object *eng2d;
struct nouveau_object *m2mf;
int nve4_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
int nvc0_screen_compute_setup(struct nvc0_screen *, struct nouveau_pushbuf *);
+int nvc0_screen_resize_text_area(struct nvc0_screen *, uint64_t);
+
+// 3D Only
+void nvc0_screen_bind_cb_3d(struct nvc0_screen *, bool *, int, int, int, uint64_t);
+
static inline void
nvc0_resource_fence(struct nv04_resource *res, uint32_t flags)
{
static inline void
nvc0_screen_tic_unlock(struct nvc0_screen *screen, struct nv50_tic_entry *tic)
{
+ if (tic->bindless)
+ return;
if (tic->id >= 0)
screen->tic.lock[tic->id / 32] &= ~(1 << (tic->id % 32));
}