return &view->pipe;
}
+struct pipe_sampler_view *
+gm107_create_texture_view_from_image(struct pipe_context *pipe,
+ const struct pipe_image_view *view)
+{
+ struct nv04_resource *res = nv04_resource(view->resource);
+ struct pipe_sampler_view templ = {};
+ enum pipe_texture_target target;
+ uint32_t flags = 0;
+
+ if (!res)
+ return NULL;
+ target = res->base.target;
+
+ if (target == PIPE_TEXTURE_CUBE || target == PIPE_TEXTURE_CUBE_ARRAY)
+ target = PIPE_TEXTURE_2D_ARRAY;
+
+ templ.format = view->format;
+ templ.swizzle_r = PIPE_SWIZZLE_X;
+ templ.swizzle_g = PIPE_SWIZZLE_Y;
+ templ.swizzle_b = PIPE_SWIZZLE_Z;
+ templ.swizzle_a = PIPE_SWIZZLE_W;
+
+ if (target == PIPE_BUFFER) {
+ templ.u.buf.first_element = view->u.buf.first_element;
+ templ.u.buf.last_element = view->u.buf.last_element;
+ } else {
+ templ.u.tex.first_layer = view->u.tex.first_layer;
+ templ.u.tex.last_layer = view->u.tex.last_layer;
+ templ.u.tex.first_level = templ.u.tex.last_level = view->u.tex.level;
+ }
+
+ flags = NV50_TEXVIEW_SCALED_COORDS;
+
+ return nvc0_create_texture_view(pipe, &res->base, &templ, flags, target);
+}
+
static struct pipe_sampler_view *
gf100_create_texture_view(struct pipe_context *pipe,
struct pipe_resource *texture,
if (!dirty)
continue;
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, 2048);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
do {
}
}
+void
+nvc0_mark_image_range_valid(const struct pipe_image_view *view)
+{
+ struct nv04_resource *res = (struct nv04_resource *)view->resource;
+ const struct util_format_description *desc;
+ unsigned stride;
+
+ assert(view->resource->target == PIPE_BUFFER);
+
+ desc = util_format_description(view->format);
+ stride = desc->block.bits / 8;
+
+ util_range_add(&res->valid_buffer_range,
+ stride * (view->u.buf.first_element),
+ stride * (view->u.buf.last_element + 1));
+}
+
void
nve4_set_surface_info(struct nouveau_pushbuf *push,
struct pipe_image_view *view,
address += lvl->offset;
info[0] = address >> 8;
- info[2] = width - 1;
+ info[2] = (width << mt->ms_x) - 1;
/* NOTE: this is really important: */
info[2] |= (0xff & nve4_su_format_aux_map[view->format]) << 22;
info[3] = (0x88 << 24) | (lvl->pitch / 64);
- info[4] = height - 1;
+ info[4] = (height << mt->ms_y) - 1;
info[4] |= (lvl->tile_mode & 0x0f0) << 25;
info[4] |= NVC0_TILE_SHIFT_Y(lvl->tile_mode) << 22;
info[5] = mt->layer_stride >> 8;
struct nouveau_pushbuf *push = nvc0->base.pushbuf;
struct nvc0_screen *screen = nvc0->screen;
- if (s == 5)
- nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
- else
- nouveau_bufctx_reset(nvc0->bufctx_3d, NVC0_BIND_3D_SUF);
-
for (int i = 0; i < NVC0_MAX_IMAGES; ++i) {
struct pipe_image_view *view = &nvc0->images[s][i];
int width, height, depth;
address += view->u.buf.first_element * blocksize;
assert(!(address & 0xff));
+ if (view->access & PIPE_IMAGE_ACCESS_WRITE)
+ nvc0_mark_image_range_valid(view);
+
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
PUSH_DATA (push, align(width * blocksize, 0x100));
PUSH_DATAh(push, address);
PUSH_DATA (push, address);
- PUSH_DATA (push, width);
- PUSH_DATA (push, height);
+ PUSH_DATA (push, width << mt->ms_x);
+ PUSH_DATA (push, height << mt->ms_y);
PUSH_DATA (push, rt);
PUSH_DATA (push, lvl->tile_mode & 0xff); /* mask out z-tiling */
}
BEGIN_NVC0(push, NVC0_CP(CB_SIZE), 3);
else
BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, 2048);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
if (s == 5)
nvc0_validate_suf(nvc0, 4);
/* Invalidate all COMPUTE images because they are aliased with FRAGMENT. */
+ nouveau_bufctx_reset(nvc0->bufctx_cp, NVC0_BIND_CP_SUF);
nvc0->dirty_cp |= NVC0_NEW_CP_SURFACES;
nvc0->images_dirty[5] |= nvc0->images_valid[5];
}
+static void
+gm107_validate_surfaces(struct nvc0_context *nvc0,
+ struct pipe_image_view *view, int stage, int slot)
+{
+ struct nv04_resource *res = nv04_resource(view->resource);
+ struct nouveau_pushbuf *push = nvc0->base.pushbuf;
+ struct nvc0_screen *screen = nvc0->screen;
+ struct nouveau_bo *txc = nvc0->screen->txc;
+ struct nv50_tic_entry *tic;
+
+ tic = nv50_tic_entry(nvc0->images_tic[stage][slot]);
+
+ res = nv04_resource(tic->pipe.texture);
+ nvc0_update_tic(nvc0, tic, res);
+
+ if (tic->id < 0) {
+ tic->id = nvc0_screen_tic_alloc(nvc0->screen, tic);
+
+ /* upload the texture view */
+ PUSH_SPACE(push, 16);
+ BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_DST_ADDRESS_HIGH), 2);
+ PUSH_DATAh(push, txc->offset + (tic->id * 32));
+ PUSH_DATA (push, txc->offset + (tic->id * 32));
+ BEGIN_NVC0(push, NVE4_P2MF(UPLOAD_LINE_LENGTH_IN), 2);
+ PUSH_DATA (push, 32);
+ PUSH_DATA (push, 1);
+ BEGIN_1IC0(push, NVE4_P2MF(UPLOAD_EXEC), 9);
+ PUSH_DATA (push, 0x1001);
+ PUSH_DATAp(push, &tic->tic[0], 8);
+
+ BEGIN_NVC0(push, NVC0_3D(TIC_FLUSH), 1);
+ PUSH_DATA (push, 0);
+ } else
+ if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) {
+ BEGIN_NVC0(push, NVC0_3D(TEX_CACHE_CTL), 1);
+ PUSH_DATA (push, (tic->id << 4) | 1);
+ }
+ nvc0->screen->tic.lock[tic->id / 32] |= 1 << (tic->id % 32);
+
+ res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING;
+ res->status |= NOUVEAU_BUFFER_STATUS_GPU_READING;
+
+ BCTX_REFN(nvc0->bufctx_3d, 3D_SUF, res, RD);
+
+ /* upload the texture handle */
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(stage));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(stage));
+ BEGIN_NVC0(push, NVC0_3D(CB_POS), 2);
+ PUSH_DATA (push, NVC0_CB_AUX_TEX_INFO(slot + 32));
+ PUSH_DATA (push, tic->id);
+}
+
static inline void
nve4_update_surface_bindings(struct nvc0_context *nvc0)
{
if (!nvc0->images_dirty[s])
continue;
- BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
- PUSH_DATA (push, 2048);
- PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
- PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
- BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 16 * NVC0_MAX_IMAGES);
- PUSH_DATA (push, NVC0_CB_AUX_SU_INFO(0));
-
for (i = 0; i < NVC0_MAX_IMAGES; ++i) {
struct pipe_image_view *view = &nvc0->images[s][i];
+
+ BEGIN_NVC0(push, NVC0_3D(CB_SIZE), 3);
+ PUSH_DATA (push, NVC0_CB_AUX_SIZE);
+ PUSH_DATAh(push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
+ PUSH_DATA (push, screen->uniform_bo->offset + NVC0_CB_AUX_INFO(s));
+ BEGIN_1IC0(push, NVC0_3D(CB_POS), 1 + 16);
+ PUSH_DATA (push, NVC0_CB_AUX_SU_INFO(i));
+
if (view->resource) {
struct nv04_resource *res = nv04_resource(view->resource);
+ if (res->base.target == PIPE_BUFFER) {
+ if (view->access & PIPE_IMAGE_ACCESS_WRITE)
+ nvc0_mark_image_range_valid(view);
+ }
+
nve4_set_surface_info(push, view, nvc0);
BCTX_REFN(nvc0->bufctx_3d, 3D_SUF, res, RDWR);
+
+ if (nvc0->screen->base.class_3d >= GM107_3D_CLASS)
+ gm107_validate_surfaces(nvc0, view, s, i);
} else {
for (j = 0; j < 16; j++)
PUSH_DATA(push, 0);
[PIPE_FORMAT_R16G16B16A16_SNORM] = GK104_IMAGE_FORMAT_RGBA16_SNORM,
[PIPE_FORMAT_R16G16B16A16_SINT] = GK104_IMAGE_FORMAT_RGBA16_SINT,
[PIPE_FORMAT_R16G16B16A16_UINT] = GK104_IMAGE_FORMAT_RGBA16_UINT,
+ [PIPE_FORMAT_B8G8R8A8_UNORM] = GK104_IMAGE_FORMAT_BGRA8_UNORM,
[PIPE_FORMAT_R8G8B8A8_UNORM] = GK104_IMAGE_FORMAT_RGBA8_UNORM,
[PIPE_FORMAT_R8G8B8A8_SNORM] = GK104_IMAGE_FORMAT_RGBA8_SNORM,
[PIPE_FORMAT_R8G8B8A8_SINT] = GK104_IMAGE_FORMAT_RGBA8_SINT,
[PIPE_FORMAT_R10G10B10A2_UNORM] = 0x2a24,
[PIPE_FORMAT_R10G10B10A2_UINT] = 0x2a24,
+ [PIPE_FORMAT_B8G8R8A8_UNORM] = 0x2a24,
[PIPE_FORMAT_R8G8B8A8_UNORM] = 0x2a24,
[PIPE_FORMAT_R8G8B8A8_SNORM] = 0x2a24,
[PIPE_FORMAT_R8G8B8A8_SINT] = 0x2a24,